This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TAS6424-Q1: Exiting Hi-Z Mode

Expert 4096 points
Part Number: TAS6424-Q1
Other Parts Discussed in Thread: PCM1690, TAS6424E

We have gotten the EVM board driving audio from my windows media play / usb through to a speaker - that's good to see the chip working with some setup.

But we are having problems getting the 6424 out of  Hi-Z mode.  A reasonable candidate is that our input TDM stream has an issue, but the 6424 doesn't show any errors or warnings.  I2C can access all the registers to read and write, but fundamentally, whenever we setup a few things (with MUTE=0, STANDBY=0)  then release MUTE and STANDBY and then put it into PLAY mode (reg 0x04) and speaker status (reg 0x0F) never ever leaves HI-Z state. 
The docs say the chip will stay in HI-Z state if there are clocking errors, but no errors are reported.  Additionally, it doesn't report that speakers are unconnected when they are unconnected.  It fundumentally feels like it's just not getting out of STANDBY or MUTE (as if the pins were held low) even though we can scope them and see they are high.

Are the MUTE/STANDBY pins different or asserted high secretly, or is there some other sequence for init?

The EVM board "just works", but that's a predefined kit and I don't know exactly what it's doing to sequence initialization.

Anyway, below is the reg address (in parens) and values.   0x04 is 0x00 for play-mode, but 0x0F is 0x55 = meaning hi-z mode.  

** amp 0 **
(00): 00 01 62 45
(04): 00 cf cf cf
(08): cf 00 11 11
(0c): 00 00 00 55
(10): 00 00 00 20
(14): 00 00 00 00
(18): 00 00 00 00
(1c): 00 00 00 00
(20): 00 00 01 14
(24): 00 00 00

  • We now see my speakers connected, and not, and we see states moving from hi-z to play, but now we see "Clock Fault Detected" on the 6424E. We fear it may be because our current design that used the PCM1690 is using LRCK=192khz with SCK/BCK=25Mhz, so 128 blocks left sync high speed as per snapshot below).

    But it looks like the 6424E only supports up to 96Khz, which in concept is fine for FSYNC=96Hz, SCK/BCK=25Mhz, so blocks of 256.   Except that's not what our FPGA is driving.

    Can you  verify this is the issue (or if not next question is how to setup for that)?  IE the FSYNC=192KHz is not supported as it was on the 1690.

  • Hi JDJ,

    The TAS6424E only supports FSYNC rates up to 96kHz. Using a 192kHz signal for the FSYNC is not supported.

    Regards,

    Ramsey