PCMD3180: PDMCLK not output and all PDM channels turned off

I shall reply shortly today

PCMD3180_2_MIC.cfg

I have included a code from our tool Pure Path Console to make 2 PCM Mikes Work. Perhaps this code can b tried .

Dear Sanjay:

Thanks your rapid response.

We just tested the code "PCMD3180_2_MIC.cfg" you provided as the following and still couldn't generate CLK out signla for pdm microphone. 

Applied the code to test and found no CLK signal output in the pcmd3180.

Although the register of ASI_OUT_CH_EN(0x74) and PWR_CFG(0x75) has enabled the PDM channel,

the value of the DEV_STS1 register is still 0x0c meaning all PDM channels turned off.

Please refer the test result is as below.

/# Power-up PDM converter and PLL by I2C write into P0_R117
//w 98 75 60
PCMD3180_write_reg(0x00,0x75, 0x60);

// # read DEV_STS1 Register
rec_reg=PCMD3180_read_reg(0x00,0x77,rec_buf);

What should we to do next step or any suggestion? 

Best Regards,

ShengHua

What timings are you giving to BCLK and FSYNC?

Dear Sanjay:

Sorry for late response. 

The ASI setting for our application is 2CH(L-CH/R-CH) with192KHz of sampling rate using I2S interface and its registers of  ASI_CFG0 and MST_CFG1 setting for pcm3180 is as the following.

Is the register setting correct? Thanks your support.

------------------------------------------------------------------------------------------------------------------------------------------------------------------

For the ASI setting of 16bits of resolution of PDM decoder at I2S mode, the value of the ASI_CFG0 Register is 0x40.

ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]

The BCLK frequency is 6.144 MHz and the ratio of BLCK to FSYNC is 32.

The setting value of the MST_CFG1 Register is 0x62.

MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]

------------------------------------------------------------------------------------------------------------------------------------------------------------------

Best Regard,

Sheng-Hua

I Shall reply shortly

Best Regards

Sanjay

Are you using the device in Slave Mode. Is the FSYNC and BCLK inputs? MST_CFG1 is only applicable for Master mode.

Is this your own board or are you using a TI Evaluation Board. Is there a chance that GPO1 pin is faulty. You could try switching over to another GPO pin for PDMCLK

Dear Sanjay:

We hope to set the device in slave mode with I2S and  the signal of  FSYNC and BCLK will be send to PDM microphone from PCDM3180.

Now we have successfully received to correct audio signal using 2CH,I2S,16bits,slave mode in the PDCM3140 EVK.

Next step we will try to port the frimware to the PCM3180 using our board,but now it still failed due to no CLK outpt to the PDM mic.

The following schematic is our pcb design for 1-CH pdm microphone. 

We will continue to study why no CLK data output ot PDM microphone.  For example, We could try switching over to another GPO pin for PDMCLK,etc. Thanks your help.

Best Regards,

Sheng-Hua

Dear Sanjay:

Sorry for late response.

We hope to configure the PCM3180 to receive the PDM microphone with 192KHz,16 bits using I2S interface.

First we followed the datasheet of PCM3180 to enable all 8 PDM channels and no PDM clock output in the PCM3180 decice. 

It is so strange that even though we have enable the register of ASI_OUT_CH_EN(0x74) and PWR_CFG(0x75), the value of the DEV_STS0 and DEV_STS1 register are 0x00 ,0x0c respectively, meaning all PDM channels are turned off.

It was supposed to get the correct setting value: DEV_STS0:0xFF and DEV_STS1:0xE0,meaning all PDM channels are turned on.

How could we do next step or any suggestion for us?

Thanks your help.

The schematic for PCM3180 is as the following.

Best Regards,

ShengHua

Hi ShengHua,

Are you using an EVM or your own board? Its possible that there is a hadrware fault of some kind .

Are BCLK and FSYNC being applied and are reaching pins of the IC?

I would also suggest to check if all supplies are reaching the IC.

Dear Sanjay:

First we tested the EVB in pcmd3140 and it can work.

Then we also tested the PCMD3180 device of our own board accord to the procedure of datasheet and it failed due to no PDM clock output.

There are four steps(S1,S2,S3,S4) to get correct digital microphone data from PC.

In first step,we measured the CLK signal(CLK1 in PCMD3180,TP12,CLK in MIC1) and found no CLK signal output to the MIC1.

How to do next step or any suggestion?

Thanks your help.

Best Regards,Sheng-Hua

Some first tests:

Is SHDNZ pin at 3.3v ?

Please check the Voltages on Vref (2.75V), AREG(1.8V),IOVDD(3.3V),AVDD(3.3V)?

Dear Sanjay:

These voltages of PCM3180 we mesaured are as the follows.

SHDNZ : 3.52V 

Vref : 2.72V , VARG: 2.0V

IOVDD: 3.52V & AVDD: 3.52V

Are they correct? 

Thanks your help.

Best Regards,Sheng-Hua

Normally we expect IOVDD /AVDD to be 3.3v and 3.6 is an absolut maximum. Why is the supply higher then 3.3v?

Areg is expected to be 1.8V

Dear Sanjay:

We remesaured these voltages by digital meter instead of digital scope and These values is correct as the following.

SHDNZ : 3.3V 

Vref : 2.72V , VARG: 1.8V

IOVDD: 3.3V & AVDD: 3.3V

Then we also tested the PCMD3180 device of our own board accord to the PCMD3180 datasheet and it failed due to no PDM clock output.

These PDM channels are supposed to be enabled after Enable Input Ch-1 to Ch-8 and Enable ASI Output Ch-1 to Ch-8.

Then we watched the DEV_STS0 register,the value was 0x00 indicating these PDM channels still powered down.

The test codes and debug information are below.

// 2024.0418 by ysh 3180 test by EVB......
//w 98 01 01
// SW_RESET
//PCMD3180_write_reg(0x00,0x01, 0x01);
PCMD3180_wr_reg(0x00,0x01,0x01);
HAL_Delay(1000);
// # Wake-up device by I2C write into P0_R2 using internal AREG
//w 98 02 81
PCMD3180_write_reg(0x00,0x02, 0x81);
HAL_Delay(1000);
rec_reg=PCMD3180_read_reg(0x00,0x02,rec_buf);
//
//# Configure CH1_INSRC as Digital PDM Input by I2C write into P0_R60
//w 98 3C 40
PCMD3180_write_reg(0x00,0x3c, 0x40);
//# Configure CH2_INSRC as Digital PDM Input by I2C write into P0_R65
//w 98 41 40
PCMD3180_write_reg(0x00,0x41, 0x40);
//# Configure CH3_INSRC as Digital PDM Input by I2C write into P0_R70
//w 98 46 40
PCMD3180_write_reg(0x00,0x46, 0x40);
//#
//# Configure CH4_INSRC as Digital PDM Input by I2C write into P0_R75
//w 98 4B 40
PCMD3180_write_reg(0x00,0x4b, 0x40);

//# Configure PDMCLK1_GPO1 as PDMCLK by I2C write into P0_R34
//w 98 22 41/40
PCMD3180_write_reg(0x00,0x22, 0x40);
//# Configure PDMCLK1_GPO2 as PDMCLK by I2C write into P0_R35
//w 98 23 41/40
PCMD3180_write_reg(0x00,0x23, 0x40);
//# Configure PDMCLK1_GPO3 as PDMCLK by I2C write into P0_R36
//w 98 24 41/40
PCMD3180_write_reg(0x00,0x24, 0x40);
//# Configure PDMCLK1_GPO4 as PDMCLK by I2C write into P0_R37
//w 98 25 41/40
PCMD3180_write_reg(0x00,0x25, 0x40);

//# Configure PDMDIN1_GPI1 and PDMDIN2_GPI2 as PDMDIN1 and PDMDIN2 by I2C write into P0_R43
//w 98 2B 45
PCMD3180_write_reg(0x00,0x2b, 0x45);
//# Configure PDMDIN3_GPI3 and PDMDIN4_GPI4 as PDMDIN3 and PDMDIN4 by I2C write into P0_R44
//w 98 2C 67
PCMD3180_write_reg(0x00,0x2c, 0x67);
//# Enable Input Ch-1 to Ch-8 by I2C write into P0_R115
//w 98 73 FF
PCMD3180_write_reg(0x00,0x73, 0xff);
//# Enable ASI Output Ch-1 to Ch-8 slots by I2C write into P0_R116
//w 98 74 FF
PCMD3180_write_reg(0x00,0x74, 0xff);
//# Power-up PDM converter and PLL by I2C write into P0_R117
//w 98 75 60
PCMD3180_write_reg(0x00,0x75, 0x60);

How to do next step or any suggestion for us?

Thanks your help.

Best Regards,Sheng-Hua

Have you tested this with another chip?

I noted that Vcc of 3.5v was reported by you. Is there a chance a High Voltage was given that resulted in damage.

Dear Sanjay:

Thanks your help.

We had tested four pieces of board and it got the same results:no PDMCLK output with 3.3V Vcc.

As for PCMD3180 datasheet,the GPO_CFG0(0x22) register,the lower byte is reserved;However, GPO_CFG0 register is set to 0x41 in the sample codes in the datasheet.

Which is correct?  Should we set the GPO_CFG0  as 0x41 or 0x40 to enable "GPO1 is configured as a PDM clock output "?

Sample codes in the PCMD3180 datasheet.

Best Regards,

Sheng-Hua

I believe 98 22 41 should be fine. I believe this would also be the setting that you programmed into the PCMD3140 EVM which then delivered a PDM Clock output.

I am inclind to believe that the software may be ok and we may have a Hardware fault.

I suggest to setup the GPO1 pin as a general purpose output and try to Write a High and Low on this pin using the GPO_VAL Register below.

This shall confirm if the I2C is working properly and the GPO pin is actually functioning.

If the GPO Pin is functioning and Toggling through I2C Command then the only reason i see an issur mey be tjhat FSYNC and BCLK signals are not proper or are not reaching the IC Pins. You should with an Oscilloscope direct check the Pins to see if these signals are reaching

Dear Sanjay: 

Thanks your help.

As you suggestion,we tried to configure the GPO_CFG0 and GPO_VAL as GPO1 in pin7 as below. 

Then we set the firmware to toggle the pin7 then measured the signal and found no signal output.

The hardware circuit is rather simple(no tied to Vdd or Ground),but no signal output in PIN7. 

PS: The device name is PDM3180.

Do you have available pdm3180 EVK for us to test? Thanks your help.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The registers were set as the following.

Toggle GPO1 in main while loop

The device name is PDM3180.

Best Regards,

Sheng-Hua

It looks to me that the I2C Commands are either not proper or the connection to I2C pins of the chip are not working.

How do you provide I2C to your Board?

Dear Sanjay:

We followed I2C command in the PCMD3180 spec and its CLK rate is 100KHz.

Then we tested SLEEP_CFG register (register address:0x02) by I2C reading and writing command.

First we writed 0x81 to address 0x02 and read the 0x02 address.

We can successfully read the correct valule:0x81. The test results is as below.

What should we do next step or any suggestion?

Best regards,

Sheng-Hua

It may be that GPIO setting is set at open drain. Can you please set for Active High and Low and then Toggle the pin. This should work and will prove that I2C as well as pin is ok.

Dear Sanjay:

As your suggestion, we set the GPIO1 register for Active High and Low and then Toggle the pin.

Then we found the toggle signal in the GPIO pin as below and prove the I2C as well as pin is ok.

We would like to configure the device to generate audio signal with 2CH(CH1/CH2) of I2S,192KHz sampling rate.

How can we configure these registers to generate ASI signal for PDM microphone as below?

Initial GPIO1 for Active High and Low and then Toggle the pin.

while loop for gpio toggle

Thanks your support.

Best Regards, Sheng-Hua

Thats great to hear. This means that I2C is working and the pin is activating,

The PDM Clock also needs the GPIO to be set to active High and Low. I would suggest to try that in the code for PDM Mic also

Dear Sanjay:

We will try to add the GPIO to be set to active High and Low to the codes,then test PDM mic.

We would like to configure the device to generate audio signal with 2CH(CH1/CH2) of I2S,192KHz sampling rate and 16/32 bits format.

How can we configure these registers to generate ASI signal for PDM microphone as below?

Could you provide the sample codes for us to test?

Best Regards,

Sheng-Hua

I would first suggest to use the I2C settings in the Datasheet With the timings associated with the I2C settings. These can be used with GPIO setting as Active High and Active low.

If you get a PDM Clock then we can adapt to another timing 

Dear Sanjay:

After adding the GPIO to be set to active High and Low to the codes,then retested PDM mic.

Then We got the same result,no PDM clock output to PDM mic.

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
# SW_RESET

w 98 01 01

delay 1sec

# Wake-up device by I2C write into P0_R2 using internal AREG
w 98 02 81

#delay 1sec

#GPIO1 to be set to active High and Low

w 98 21 11

#
# Configure CH1_INSRC as Digital PDM Input by I2C write into P0_R60
w 98 3C 40
#
# Configure CH2_INSRC as Digital PDM Input by I2C write into P0_R65
w 98 41 40
#
# Configure CH3_INSRC as Digital PDM Input by I2C write into P0_R70
w 98 46 40
#
# Configure CH4_INSRC as Digital PDM Input by I2C write into P0_R75
w 98 4B 40
#
# Configure PDMCLK1_GPO1 as PDMCLK by I2C write into P0_R34
w 98 22 41
#
# Configure PDMCLK1_GPO2 as PDMCLK by I2C write into P0_R35
w 98 23 41
#
# Configure PDMCLK1_GPO3 as PDMCLK by I2C write into P0_R36
w 98 24 41
#
# Configure PDMCLK1_GPO4 as PDMCLK by I2C write into P0_R37
w 98 25 41
#
# Configure PDMDIN1_GPI1 and PDMDIN2_GPI2 as PDMDIN1 and PDMDIN2 by I2C write into P0_R43
w 98 2B 45
#
# Configure PDMDIN3_GPI3 and PDMDIN4_GPI4 as PDMDIN3 and PDMDIN4 by I2C write into P0_R44
w 98 2C 67
#
# Enable Input Ch-1 to Ch-8 by I2C write into P0_R115
w 98 73 FF
#
# Enable ASI Output Ch-1 to Ch-8 slots by I2C write into P0_R116
w 98 74 FF
#
# Power-up PDM converter and PLL by I2C write into P0_R117
w 98 75 60

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

Best Regards,

Sheng-hua 

Was there a BCLK and FSYNC applied to the device for this test?

Additionally would you please also try toggling the GPO pin ? I believe the GPIO pin has been toggled

Dear Sanjay:

It is good news, the toggle of GPIO1 and GPO1 has successed.

After configuring the audio CH1/CH2,how should we set BCLK and FSYNC for I2S,16/32 bits,192KHz of sampling rate?

As for BCLK and FSYNC were applied to the device,which registers have be set for test?

Could you provide sample codes for us to test?

 - Audio Channel: CH1/CH2,

 - I2S format,16/32 bits,192KHz sampling rate

Best Regards, Sheng-Hua

------------------------------------------------------------------------------------------------------------------------------------------------------

The GPO1 toggle test flow as below.

First we just tested two kinds of mode GPO_CFG0 seting to test GPO toggle function.

case1: GPO_CFG0(0x22):0x10 , GPO toggle failed.(the voltage of GPO is low)

case2: GPO_CFG0(0x22):0x11 , GPO1 toggle successed

According to the datasheet, the lower 4 bits of the register GPO_CFG0 are reserved.

In order to let GPO1 toggle, we must set the lower bits of GPO_CFG0 as "drive active low and active high" like GPIO_CFG0 register.

.Normally ASI _CFGO sets the protocol and number of bits.

We operate in slave mode then we need to externally apply BCLK and FSYNC to the chip.

The chip has an auto clock mechanism that internally sets up the chip if valid incoming timing is given to the chip .

Steps:

1.Load the I2C as given in datasheet. Enable GPO as done above

2.I would suggest to give FSYNC of 44.1Khz and BCLK of 11.2896 to the device as a first step . (the 192K can be given later)

3. Check if PDM Clock appears. If not appearing see ASI_STS register to determine

if the timing is reaching the chip pins ok.

Dear Sanjay:

We will try later. Thanks you support.

Best Regards,

Sheng-Hua

sure.

Regards

Sanjay

Dear Sanjay:

Sorry for late response.

We followed the test steps as you suggested and finally got correct mic data.

Now we operate in slave mode then we need to externally apply BCLK and FSYNC to the chip.

Steps:

1.Load the I2C as given in datasheet.

ASI Configuration: I2S,32 bits mode,CH1/CH2,48KHz sampling rate

# CHECKSUM 0
# Generated by PCMD3180-SW v3.0.1
# PCMD3180 device configuration
# -----------------------------------------------------------------------------
# Reset
# -----------------------------------------------------------------------------
# Select Page 0
w 98 00 00
# Reset Device
w 98 01 01
# 1mS Delay
# -----------------------------------------------------------------------------
# Begin Device Memory
# -----------------------------------------------------------------------------
# Page 0 (0x00) Dump
# Select page 0
w 98 00 00
# Wake up and enable AREG
w 98 02 81
# ASI Configuration: I2S,32 bits mode
w 98 07 70

# Configure CH1_INSRC as Digital PDM Input by I2C write into P0_R60
w 98 3C 40

# Configure CH2_INSRC as Digital PDM Input by I2C write into P0_R60
w 98 41 40

# Configure PDMCLK1_GPO1 as PDMCLK by I2C write into P0_R34
w 98 22 41

# Configure PDMDIN1_GPI1 as PDMDIN1 by I2C write into P0_R43
w 98 2B 40

#PDM Input Channel/2 Enable
w 98 73 c0
#ASI Output Channel/2 Enable
w 98 74 c0

# Power-up PDM converter and PLL by I2C write into P0_R117
w 98 75 60

# Apply FSYNC = 48 kHz and BCLK = 3.072 MHz and
# Start recording data by host on ASI bus with I2S protocol 32-bits channel wordlength

2.apply FSYNC of 48Khz and BCLK of 3.072MHz to the device as a first step .

After apping the BCLK is 3.072 MHz and the FSYNC = 48 kHz,we found the PDM clk successfully output to PDM mic.

3. Check if PDM Clock appears. If not appearing see ASI_STS register to determine

The ASI status register is 0x44 as the datasheet description.

Finally,we tried to test the audio data,it can be recorded correctly.

Below is mic record result using the audacity tool.

Thanks your help.

Best Regards,

Sheng-Hua