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TPA3116D2: AVCC vs. PVCC Connectivity on the TPA3116/TPA3130/TPA3118 family of devices

Part Number: TPA3116D2

TI Team, 

The data sheet for these devices mentions that it is customary to tie the AVCC pins and PVCC pins together on the board to the same voltage net. However, what happens if we don't tie them to the same net? We can see in the block diagram in the data sheet that the AVCC pin is taken internally to an LDO which creates both the AVDD power supply for use by the low-voltage audio section of the IC and the gate drive voltage (GVDD) used to drive the gate of the output power devices.  Is it the case that AVCC must be held to the same voltage potential of the PVCC net? If not, is it important to ensure that the PVCC pins are held at a higher voltage potential than the AVCC pin? ... or at a lower potential? Can we drive them at two different voltage potentials if we so choose?

It seems that if we are using a TLV/PCM DAC component with a 3.3V output voltage buffer stage (with commensurate charge pump to create a negative 3.3VDC supply providing a zero-centered output from the DAC), we should only need to provide a well regulated 7-12VDC power supply to AVCC- right? This should be true regardless of what voltage we are running PVCC at- correct?

The PVDD net we're supplied in the system is a bit noisy and full of charging current for the bulk capacitances, so we'd like to drive the analog front end of the TPA31xx devices from a separately regulated "clean" power supply. Do you see any issue with us doing that? 

Thanks in advance for your feedback- 
Cody

  • Hi Cody

      No problem about your using. AVCC and PVCC could use different power supply, and AVCC only provide for internally LDO, could consider using smaller value to decrease power loss. PVCC provide the output power, select according to your output requirement. It doesn't matter which one has higher voltage.