TLV320AIC3100: TLV320AIC3100

Hi Bruce,

The TLV320AIC3100 by default is set to receive the MCLK, BCLK, and WCLK from an external source. No changes are needed there. The Init Script is just a txt file that gets loaded up; it's not reactive to your changes. However you can use the init script as a starting example for what you want to achieve.

Best regards,
Jeff McPherson

Jeff,

What other settings are "defaults"?
If I do not send an Initialization Script, will the device pass audio?  Will it turn on the Class D amp? Will it use 24bit word length?

Of all the commands that the Codec Control initialization creates, which ones do I need to get this device to pass audio from mic input to speaker output ?

Hi Bruce,

If you don't send a script, the device is functionally in a standby state: the device has power but all of the audio signal chain is powered down. 

By default the device is set for 16 bit word length as shown in the picture below. You can read through the register map to find all the default settings. I'll address your below question in a moment.

Best regards,
Jeff McPherson

This is the configuration that I want.

Do I need to power the Internally generated BCLK if I am clocking MCLK, BCLK and, LRclk extrenally?  (red circle)

How would I get the script for these desired settings without toggling each edit box separately and recording in the Command Buffer window?
Is there any way to shortcut this process?

Hi Bruce,

No, you don't need to power on internal BCLK nor the PLL if you're providing clocks externally.

The simplest steps in order to get a mic input -> speaker output is to use the analog bypass path using page 1 register 35. 

Set the bypass path, power up the speaker driver and set the volume. That should be all you need to do with the exception of adjusting for your clock settings.

If you want to go through the entire signal flow, you can use the loopback options (fyi these don't appear in the GUI as any clickable switch) 

After powering on the ADC, DAC, and setting the signal path, you can use these loopback options to either short the DIN DOUT pins together or internally connect the ADC output to the DAC input. 

As far as shortcutting the command window, if you hover over a switch in the GUI, the corresponding register (in decimal) and current value of the register appear in the bottom of the screen near the "EVM Activity" light. 

Best regards,
Jeff McPherson

Is there any particular order in which the registers should be set?  What about the order of powering on the different subsystems?

Hi Bruce,

The order is mostly tolerant of any order you choose. For best practices I would set connections first before powering on any blocks (set mic input to ADC, DAC output/bypass path to speaker etc) and power on and unmute the speaker last. This will help avoid popping sounds.

Best regards,
Jeff McPherson

Jeff,

I have reworked my initialization code and still do not have audio.
I have tried analog loopback, beep into DAC output and still no go.

I know that I am talking to the device since I can see the Class D outputs (PWM) come on after the last init command.
The HP outs also show a small pop when the init runs.

Could you please check what I have here and see if I am missing something?
I am not sending some of to the registers that already have the proper default (reset) value.

Is there any other way (programmatically) to see if the ADC chain is getting input?
My DSP is not seeing any input.

Please advise,

WORD CinitWord[57] = {
                    0x0000,                    // * Reg 0    -------- Select Page 0         --------
                    0x0101,                    // Reg 1        s/w reset
                    0x0400,                    // * Reg 4        PLLin = MCLK pin, CodecClk = MCLK pin
                    0x0B81,                    // Reg 11        DAC NDAC div 1, power on        
                    0x0C82,                    // Reg 12        DAC MDAC div 2, power on    
                    0x0D00,                    // Reg 13        DAC DOSR MSB    
                    0x0E80,                    // Reg 14         DAC DOSR LSB
                    0x0F20,                    // Reg 15        DAC IDAC
                    0x1004,                    // Reg 16        DAC PRB Engine Interpolation    ???
                    0x1281,                    // Reg 18        ADC NDAC div 1, power on
                    0x1382,                    // Reg 19        ADC MDAC div 1, power on
                    0x1400,                    // Reg 20        ADC DOSR MSB
                    0x1580,                    // Reg 21        ADC DOSR LSB
                    0x1620,                    // Reg 22            ??
                    0x1704,                    // Reg 23            ??
                    0x1B20,                   // Reg 27         I2S,wordlength 24
                    0x4100,                    // Reg 65        DAC gain left 0db
                    0x4200,                    // Reg 66        DAC gain right 0db    
                    0x4400,                     // Reg 68          DRC disable, th and hy                                
                    0x7400,                    // Reg 116        DAC => volume control thru pin disable
                    0x0001,                    //         -------- Select Page 1 ------------
                    0x214e,                     // De-pop, Power on = 800 ms, Step time = 4 ms
                    0x1fc2,                     // HPL and HPR powered up
                    
                    0x2344,                    // LDAC routed to HPL, Class D; RDAC routed to HPR
                    0x280E,                    // HPL unmute and gain 1db,
                    0x290E,                    // HPR unmute and gain 1db
                    0x2400,                    // No attenuation on HP
                    0x2500,                    //
                    0x2600,                    // Class D Atten = 0
                    0x2A1C,                 // Class D +24db gain
                    
                    0x2e0b,                    // MIC BIAS = AVDD
                    0x2F80,                    // ADC PGA 0x80 = 0db 0x0B = +24db
                    0x3040,                    // MICPGA P = MIC 10k
                    0x3140,                    // MICPGA M - CM 10k
                    0x0000,                 //         -------- page 0 is selected         --------
                    0x3c0b,                 // select DAC DSP mode 11 & enable adaptive filter
                    0x0008,                 //
                    0x0104,                 //
                    0x0000,                 //
                    0x3fd6,                    // POWERUP DAC left and right channels (soft step disable)
                    0x4000,                 // UNMUTE DAC left and right channels
                    0x5180,                    // POWERUP ADC channel
                    0x5200,                    // UNMUTE ADC channel
                    0x0001,                 //         --------  page 1 is selected         --------
                    0x2a1c,                 // Unmute Class-D Left
                    0x2b1c,                 // Unmute Class-D Right
                    0x20c6,                    // Power-up Class-D drivers
                    0x0000,                 // ------------- Page 0 --------------
                    0x4700,                    // Reg 71 beep
                    0x4800,
                    0x4900,
                    0x4A56,
                    0x4B22,
                    0x4C11,
                    0x4DF5,
                    0x4E7E,
                    0x4FBA
                    };
                       

Hi Bruce,

I have an EVM that I can use to mimic your setup to try to help narrow down the issue. Nothing jumps out at me from looking at your script. 

While I study your code further, when you say the DSP is not seeing any input, are you getting any activity from the DOUT pin or is it totally flat? If it is toggling that means that the ADC is enabled and most likely getting the right clocks.

Thanks,
Jeff McPherson

I will check the data lines. 

Hi Bruce,

I'm attaching below a script that I used to get analog in, analog out. It is based off the EVM initialization script with just a few additional lines. To get the Class D volume up and do connect the analog bypass loop. I'm attaching the whole script for your reference but you will likely need to change the clocking values at the beginning to make them match. But at least this will guarantee that the signal flow should be correct.

As I was building this I noticed that you aren't setting register P1/R38. This is an attenuator before the class D driver that by default is set to -78dB. Even though the Class D was powered up correctly and you saw the PWM wave, without setting register 38, you won't see your signal. This is the first thing I would fix, but I'll give you the script I was mentioning anyway so that you have a working reference.

#			--------------------------------------------------------------- page 0 is selected 
w 30 00 00
#			 s/w reset
w 30 01 01
#			 PLL_clkin = BCLK,codec_clkin = PLL_CLK
w 30 04 07
w 30 05 91
w 30 06 20
w 30 07 00
w 30 08 00
#			 mode is i2s,wordlength is 16
w 30 1b 00
#			 NDAC is powered up and set to 4
w 30 0b 84
#			 MDAC is powered up and set to 4
w 30 0c 84
w 30 12 84
w 30 13 84
#			 DOSR = 128, DOSR(9:8) = 0
w 30 14 00
#			             DOSR(7:0) = 128
w 30 15 80
#			 CLOCKING ENDS HERE
#
#			 DAC => volume control thru pin disable 
w 30 74 00
#			 DAC => drc disable, th and hy
w 30 44 00
#			 DAC => 0 db gain left
w 30 41 00
#			 DAC => 0 db gain right
w 30 42 00
#			--------------------------------------------------------------- page 1 is selected
w 30 00 01
#			 De-pop, Power on = 800 ms, Step time = 4 ms
w 30 21 4e
#			 HPL and HPR powered up
w 30 1f c2
#			 LDAC routed to HPL, RDAC routed to HPR
w 30 23 44
#			 HPL unmute and gain 1db
w 30 28 0e
#			 HPR unmute and gain 1db
> 0e
#			 No attenuation on HP
w 30 24 00
w 30 25 00

#			 MIC BIAS = AVDD
w 30 2e 0b
#			 MICPGA P = MIC 10k
w 30 30 40
#			 MICPGA M - CM 10k
> 40
#			--------------------------------------------------------------- page 0 is selected
w 30 00 00
#			 select DAC DSP mode 11 & enable adaptive filter
w 30 3c 0b
w 30 00 08
w 30 01 04
w 30 00 00
#			 POWERUP DAC left and right channels (soft step disable)
w 30 3f d6
#			 UNMUTE DAC left and right channels
w 30 40 00
#			 POWERUP ADC channel
w 30 51 80
#			 UNMUTE ADC channel
w 30 52 00
#			--------------------------------------------------------------- page 1 is selected
w 30 00 01
#			 Unmute Class-D Left
w 30 2a 1c
#			 Unmute Class-D Right
w 30 2b 1c
#			 Power-up Class-D drivers
w 30 20 c6
#			 Connect MIC1LP and MIC1RP to Speaker Outputs
w 30 23 54
w 30 23 74
#			 Set analog attenuator to Class D output to 0dB
#			 The GUI recorded the same write twice
#			 Likely a bug in the gui but im leaving it incase it is necessary			 
w 30 26 00
w 30 26 00

Best regards,
Jeff McPherson

Regarding :  "I noticed that you aren't setting register P1/R38. "

                    0x2400,                    // No attenuation on HP
                    0x2500,                    //
                    0x2600,                    // Class D Atten = 0
                    0x2A1C,                 // Class D +24db gain

This is in my init script.
                    

Sorry about that. I got the hex and decimal addresses mixed up and misread your script. Regardless, how is the testing going with information I gave?

I confirmed that the ADC is seeing audio input and DOUT data is changing with that input. 

I think I might need to swap Left and Right channels in the data stream so that my DSP sees the data. 

I see Iin the data sheet that the ADC mono input is transmitted on both left and right phases of the I2S stream. Is that correct?

I will get a digital scope on MCLK, LRclk and DOUT to confirm that I am getting the correct timing. 

I notice that the logic level spec for the ADCout is Voh (0.8 x IOVdd)
I am measuring it at about 2.45V for a 3.3V IOVdd

My DSP logic input has a minimum Vih of 2.0V

Why is this I2S output level so low?

Hi Bruce,

Yes, the device is "dual mono" meaning it will have the same data on both the left and right channels from the mono ADC.

0.8 of 3.3 (assuming a perfect 3.3V supply) is ~2.6V so 2.45V is within reason. If the minimum high of the DSP is 2V, then the I2S data should clear that threshold pretty easily.

When you say "output level is low" are you still talking about the logic level or do you mean the audio volume?

Thanks,
Jeff McPherson

Logic level. My DSP still doesn’t see incoming data. Since the data rate is controlled by the DSP (master) what else could keep the DSP from recognizing data?  I monitor both left and right channels of the I2S stream. When we used the TLV320AIC23b it worked fine. Same board. Just depopulated the AIC23b section and populated the AIC3100

Hi Bruce,

Is your DSP set to expect the same format as the codec is set to? Likely this is standard I2S format. If you're worried about the logic level, can the threshold be adjusted, or is it fixed?

I see on your scope that the data is AC coupled. If you DC couple it, is there any offset that may be responsible for violating the logic thresholds?

Also I'm not sure the AIC23B and AIC3100 are pin to pin compatible. Looking at the pinouts, they are quite different.

(AIC23B)

(AIC3100)

I'm not sure how you got the device working without changing any of the layout, so can you confirm that the DOUT pin is connected to the correct DSP port?

Thanks,
Jeff McPherson

The 2 different devices have totally separate areas of the circuit board. 

I was only commenting on the logic levels and looking for some clue about why I could not detect ADCdata from the 3100

Hi Bruce,

Gotcha. I'm not an expert on the DSP, but if it's a TI device I can point you to that team.

Like I mentioned before, I would measure the DOUT with DC coupling to ensure the exact logic levels, rather than the relative ones. I would also double check the I2S format settings on both the codec and DSP to make sure they match. Sometimes if the format being received is unexpected the input is just disregarded. 

I am seeing that the DOUT pin of the AIC3100 is only pulling up to ~2.4V for a data high when working with a 3.3V system.

Is it acceptable to add anexternal  pull-up resistor to get that Voh up closer to 3.3V?

Hi Bruce,

I was mistaken earlier, the minimum output level for this device at 3.3V should be 2.6, so 2.4V is out of spec. How are you measuring the DOUT pin? Can you disconnect it from your DSP and let it float when you take the measurement (DC coupled)?

Thanks,
Jeff McPherson

Disconnecting it from the DSP allows it to reach Voh = 3.3V

I will look into the settings of the DSP to see why this is the case.

The thing that I don’t understand is that the main code base for the DSP is identical between the board using the AIC23b and the one using the AIC3100. 

The 23b works fine and the Dout signal level pulls all the way up to 3.3v

Is this just a matter of drive capacity on the 3100?

Hi Bruce,

I agree it's probably a drive strength problem. I'm not sure of the exact limitations since the data sheet doesn't list it explicitly in terms of current, but I would try raising the input impedance of your DSP pin receiving DOUT. The current provided by the AIC3100 is probably not enough to get the load near 3.3V with the impedance you have set.

Best regards,
Jeff McPherson