PCM1865: PCM1865 SCKI Ratio / PCM1681 SCK Ratio

shuji kiyama

Prodigy 60 points

Part Number: PCM1865
Other Parts Discussed in Thread: PCM1681

Hello, experts.

The data sheet states that the ratio of externally supplied master clocks (SCKI) to the PCM1865 should be 48%~52%.

In addition, the data sheet states that the ratio of externally supplied clocks (SCK) to the PCM1681 should be 40%~60%.

Is it a problem if the clock (SCKI or SCK) deviates significantly from this ratio only about once every 10 seconds?

（PCM1865 is used with SCKI=BCK, and PCM1681 is used with SCK=BCK.）

As long as you listen to the audio in this state, there is no problem.

7 months ago

0 shuji kiyama 7 months ago

Prodigy 60 points

Hello, experts.

It will be a supplement.

The ratio of BCK changes in the same way as SCKI or SCK.

0 Sanjay Dixit 7 months ago in reply to shuji kiyama

TI__Mastermind 23030 points

Can you please specify the Timings provided to the chip?

0 shuji kiyama 7 months ago

Prodigy 60 points

Hi, Sanjay Dixit

For PCM1865, 4.096 MHz is input with SCKI = BCK, and 16 KHz is input to LRCK.

BCK and LRCK are synchronized to SCKI.

The same applies to PCM1681, where 4.096 MHz is input at SCK = BCK and 16 KHz is input at LRCK.

BCK, LRCK, and DATA are synchronized to SCK.

0 Sanjay Dixit 7 months ago in reply to shuji kiyama

TI__Mastermind 23030 points

I am looking into this. Please expect a response in a few hours.

0 Sanjay Dixit 7 months ago in reply to Sanjay Dixit

TI__Mastermind 23030 points

As long as the BCk High time is greater then 65ns , it shoul be ok.

At BCLK=4.086MHZ, O.52

0 Sanjay Dixit 7 months ago in reply to Sanjay Dixit

TI__Mastermind 23030 points

As long as the BCk High time is greater then 65ns , it shoul be ok.

At BCLK=4.086MHZ, 0.52*TBCLK IS 12ns. This is higher then the 65ns lower limit

0 shuji kiyama 7 months ago

Prodigy 60 points

Thank you. Sanjay Dixit

Let me confirm a little more.

If the timing requirements of the BCK are satisfied, even if the ratio of Hgih time to Low time of the SCK (Master Clock) is not satisfied,

Is it okay to understand that there is no problem?

0 Sanjay Dixit 7 months ago in reply to shuji kiyama

TI__Mastermind 23030 points

What is the Maximum deviation in the duty cycle of SCLK ?

0 shuji kiyama 7 months ago

Prodigy 60 points

Hi, Sanjay Dixit

Sorry for the late reply.

There seems to be a misunderstanding, so I will attach a block diagram and a waveform.

At 16kHz intervals, the high period of SCK(or SCKI) and BCK is lengthened or shortened by one pulse.

Will this be a problem?

+1 Daveon Douglas 7 months ago in reply to shuji kiyama

TI__Mastermind 19150 points

Hi Shuji,

Thank you for providing the diagram. If your BCLK is being lengthened or shortened by one pulse, you risk losing the data read at the falling edge of BCLK.

My suggestion to eliminate this problem, is to only provide SCLK and use the PLL to generate the lower jitter ASI clocks. In this method, through internal dividers, BCLK and LRCLK will be in sync with the source clock.

If you know exactly when this deviation in pulse will occur. You can create buffer channel slots so the data will read empty channels. For instance, if you need 2 channels but you provided timing for 4 channels, the deviation in pulse will read the subsequent empty data slots that are appended with 0's.

Regards,

0 shuji kiyama 7 months ago

Prodigy 60 points

Thanks, Daveon,

I will respond with the latter proposal.

Thank you for your quick response.

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PCM1865: PCM1865 SCKI Ratio / PCM1681 SCK Ratio