My customer is looking at PCM1681 for a non-audio application. The data output rate to the DAC channels would be <= 20kHz. Could you please help with the following:
- Would it be possible to disable any intermediate processing blocks and just feed the I2S data straight to the output?
- Brian: I see de-emphasis, roll-off, and digital attenuation can be disabled. Is there anything else that might need to be and can be disabled to make this a "normal" DAC?
- On page 18 it is showing TDM mode where you can feed all 8 channels using a single data input, which is what my customer would want to use. Their question lies with the LRCK signal. Would it be possible to just use a standard I2S peripheral output that drives LRCK 32 bits high (left), 32 bits low (right)? The entire 8 channel frame would be:
- 32 bits LRCK high (CH1)
- 32 bits LRCK low (CH2)
- 32 bits LRCK high (CH3)
- 32 bits LRCK low (CH4)
- 32 bits LRCK high (CH5)
- 32 bits LRCK low (CH6)
- 32 bits LRCK high (CH7)
- 32 bits LRCK low (CH8)
Figure 24 seems to show LRCK being a don’t care after the first clock edge up until the last clock edge, where it must be low. This would be covered with step (a) and step (h) above. The customer's MCU does not have a peripheral that can support a LRCK signal that outputs a single pulse every 32 bits. However, it does have a standard I2S port.
Thank you,
Brian
