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TLV320AIC3106: Not connecting MCLK

Dean Hofstetter
Expert 2565 points
Part Number: TLV320AIC3106

We require that the 3106 be configured as the slave.  The processor will be the master of the audio bus, in this case a Renesas RZ/G2L processor.

Section 10.3.3.1 of the 3106 datasheet implies that all internal clocking can be provided by BCLK, and thus MCLK would be not needed.  Is it possible to configure the 3106 to NOT use MCLK at all, and if so would we simply connect MCLK to GND?

Thanks, Dean

  • +1
    TI__Mastermind 31455 points

    Hi Dean,

    Yes you're correct. In slave mode, MCLK is not required and the clock tree can be set up such that BCLK is used instead. MCLK should be AC coupled to GND with a small capacitor to help prevent any noise from getting into the codec as opposed to directly connecting it to GND.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Expert 2565 points

    Thanks for that confirmation.  One more question.  This will be an embedded Linux project.  Does the Linux driver support this hardware configuration?

    - Dean

  • 0 in reply to Dean Hofstetter
    Expert 2565 points

    I should have specified that our application uses 8kHz data at 16 bits.  The internal CODEC_CLK for the 3106 must be 256 x Fsref, where Fsref is either 48kHz or 44.1kHz.  We use 48kHz, so the internal CODEC_CLK is 12.288MHz.  If we choose to not use the PLL, then the smallest Q value we can use is 2 (which means don't divide CLKDIV_IN at all).  Since CLKDIV_IN = BCLK = 12.288MHz.  We were trying to save sending a long clock trace across our PCB in the MHz range, but it doesn't seem to matter if we use MCLK or BCLK.  If we use MCLK at 12.288MHz, then BCLK will be in the 256kHz range.  No hardware configuration exists where a MHz clock isn't required.

    Thanks anyway.

  • 0 in reply to Dean Hofstetter
    TI__Mastermind 31455 points

    Hi Dean,

    I'm not super experienced with the driver but I believe that it does, since by default the device should auto select between MCLK and BCLK ports for the PLL. If not you can make edits to the driver yourself, or you can reach back out here for support.

    Thanks,
    Jeff McPherson