TLV320AIC3204EVM-K: AGC:Audio compression curve

Luo Lu

Tool/software:

Hello, now I need to reduce the gain effect, that is, the compression curve as a whole. Do I only need to modify the parameters of AGC to achieve this? If not, what else should be changed? P1 is the current compression curve and P2 is the compression curve that needs to be achieved.

Parameter configuration of AGC parameters:

TLV320AIC3204EVM-K: About the AGC loop - Audio forum - Audio - TI E2E support forums

If it is convenient, you can tell me how to modify the parameters of AGC. Thank you very much!

Can you help to solve it

thanks

over 1 year ago

0 Luo Lu over 1 year ago

Prodigy 240 points

high resolution image

0 Daveon Douglas over 1 year ago in reply to Luo Lu

TI__Mastermind 27710 points

Hi Luo,

P1 (114dB) and P2 (96dB) have different output levels. Are you trying to achieve the same output level, if so this can be achieved in the AGC algorithm by adjusting the target level. If you are trying to change the rate at which the AGC engages you will have to change the attack/decay time.

Using the AGC,DRC and Beep generator Function in TLV320AIC3204/3254/3100/3110/31

Regards,

0 Luo Lu over 1 year ago in reply to Daveon Douglas

Prodigy 240 points

I lowered the output level and finally reached the output of 96db, but the first part is also compressed, I want the first part of the output is amplified, and the second part reaches 96db and then stays at 96db. What should I do? Please help me answer, thank you.

Regards.

0 Daveon Douglas over 1 year ago in reply to Luo Lu

TI__Mastermind 27710 points

Hi Luo,

To better analyze response of the device. Can you provide a measurement of input signal level (Vrms, Vpp, or Vp) vs output signal level.

If we're trying to debug AGC response, its better to analyze signal level comparison like below:

Also, how does the output signal respond with AGC disabled, if you can share an FFT or frequency sweep (frequency vs RMS (dBFS) level) would be helpful.

Regards,

0 Luo Lu over 1 year ago in reply to Daveon Douglas

Prodigy 240 points

Hi Daveon，

I would like to know how to configure registers when AGC and DRC are used simultaneously.？

Regards.

0 Daveon Douglas over 1 year ago in reply to Luo Lu

TI__Mastermind 27710 points

Hi Luo,

Yes this is possible, the AGC is present in the ADC signal path and the result is reflected through the DOUT pin. The DRC algorithm is present in the DAC signal chain, result shown in the analog output. Configuring both is explained in the application note I linked in my previous message.