TLV320ADC6140: SDOUT has no output data waveform, while FSYNC and BCLK have outputs

Part Number: TLV320ADC6140


Hello everyone:

At present, I am using the arm linux platform to adapt tv320adc6140. The hardware design is based on the design in the chip manual. The mic pickup (differential analog input) input chip has a normal data waveform, while the sdout of the chip has no normal output data waveform.

The tlv320adc6140 works in master mode, according to the active mode description in the chip manual and the evm demo:

Should only need: Power on, reset, wake up, configure other registers according to actual requirements, configure channel enable (IN_CH_EN, ASI_OUT_CH_EN) at the end, and configure PWR_CFG register to turn on the power supply. After turning on the power supply, you can check the power supply status through DEV_STS0 and DEV_STS1. Now, after the power supply is turned on through the driver configuration (or manually configured in user space), it is found that all channels are in the state of disable and power down after reading the two status registers directly. The status of the registers is as follows:

It can be seen that IN_CH_EN, ASI_OUT_CH_EN, and PWR_CFG are opened with operations, but DEV_STS0 and DEV_STS1 think that the channels are in the disable and active power down states. In this case, which aspects should be checked?


  • Hi,

    In master mode, when SDOUT has distortion and the FSYNC and BCLK output is correct, this can be a symptom of incorrect ASI bus format or the input signal is violating the input pin parameters of the ADC. My comments:

    1. What is your MCLK signal? What is the measured BCLK and FSNYC output?

    2. Can you provide a oscilloscope snip of your input signal? Ensure this signal does not exceed 2Vrms for a differential input.

    3.  Your register configuration is configured for I2S, so its important your digital receiver that is analyzing SDOUT is configured to read at 4 CH, 16-bit word length


  • Thank you for your reply.

    1.I am using an integrated, low-jitter, phase-locked loop (PLL), 0x13 register is 0x81, and fsync is around 13M

    2.This is the waveform of 1Khz sine wave input, after mic to in1p

    3.Yes, I use 4-channel, 16bit on the arm side, and the command is arecord -D hw:1,0 -r 48000 -f S16_LE -c 4 test.wav.

    But strange, why is the content of DEV_STS0 and DEV_STS1 channel disable, power down? The configuration of the IN_CH_EN, ASI_OUT_CH_EN and PWR_CFG registers is clearly opened with the Settings

  • Hi,

    Change 0x13 register value to 0x82 if MCLK input is 13MHz. Change BCLK:FSYNC ratio to be 64 in register 0x14; value = 0x44. Then verify output FSYNC is 48kHz, BCLK = 3.072MHz.

    BCLK should equal 4CH * 16bit word length, * 48k FS = 3.072MHz.


  • I don't have a mclk. The fsync pin output is 13M. I use pll to provide the clock internally and I don't use GPIO1 or GPIx for the mclk input

  • Hi,

    You're trying to configure device for master mode, correct? Also, FSYNC is only supported from 8k - 768kHz.

  • Sorry, I made a mistake before. bclk is about 13M

  • Ok, please read: 

    Configuring and Operating TLV320ADCx140 as Audio Bus Master

    To ensure you setting device up correctly. The GPIO pin must be configured at MCLK and you, the host, must provide this signal for the device operate in master mode. Your high frequency signal will then generate the lower jitter ASI clocks.

  • I feel very strange now, when I reset the chip, all the registers are in the default state, at this time I wake up the chip (set 0x02 register to 0x81), turn off all the power (set 0x75 to 0x00), open all the channels (set 0x73 register to 0xf0), power up all (set 0x75 to 0xe0), why is the content of the DEV_STS0 register 0x00?
    In TI-TLV320ADC6140.pdf, chapter " Example Device Register Configuration Script for EVM Setup" is also operated in this way.
    Does the DEV_STS0 register not return information correctly or is the channel in a disabled state?

  • If I use pll, do I need an external reference clock for this chip?
    “ The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the ADC modulator and digital filter engine, as well as other control blocks.”
    As described in the chip manual above, I don't need an external mclk in master mode? Just configure to enable pll.

  • According to this(sbaa382.pdf (, through gpio1 input 12Mhz crystal oscillator, fsync and bclk can output normally, can be measured up to 12.288Mhz and 48Khz , but sdout can only output up to 1v signal, this is the register configuration problem?