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TAS6424E-Q1: Tas6424 keeps reporting invalid clock error

yaoxuefeng yaoxuefeng
Prodigy 10 points
Part Number: TAS6424E-Q1
Other Parts Discussed in Thread: TAS6424

Tool/software:

The TDM clock and data of Tas6424 are output by the Soc side.

The format of the wav file played by the Soc side is 8 channels, 32 bits, and a sampling rate of 48000.

The input pins of the amp are measured with an oscilloscope, and Bclk, FSclk, and Data are all correct.

In addition, the following power supply pins of Tas6424 are also measured correctly, and the results are as follows:

VBAT/PVDD are both 12V

VDD is 3.3V

Pins: Standby and Mute are also measured at high levels.

1. After power on, set the Standby and Mute pins of tas6424 to high level.

2. Then set the following registers:

1) SAP Control (Serial Audio-Port Control) Register (address = 0x03) Set to 0x46 (other values ​​such as 0x44, 0x45, 0x43 have also been tried, and the results are the same)

2) Channel State Control Register (address = 0x04) Set to 0x0;

Then the software follows the process of the Note prompt in datasheet:10.2.1.2.2 Digital Input and the Serial Audio Port

But as long as the Channel State Control Register (address = 0x04) is set to 0x0 (Play state), the value of Global Faults 1 Register (address = 0x11) will become 0x10 (i.e.: INVALID CLOCK), The software will use Bit7 (CLEAR) of Miscellaneous Control 3 Register (address = 0x21) FAULT) to clear the error;

1) If the Soc side does not play the wav file, the value of the Channel State Reporting Register (address = 0x0F) is the default value 0x55 (Hi-Z state);

2) If the Soc side is playing the wav file, the value of the Channel State Reporting Register (address = 0x0F) will become 0xAA (Mute state);

the value of the Global Faults 1 Register (address = 0x11) will become 0x0. Until the end of the playback

3) After the Soc side finishes playing, the value of the Channel State Reporting Register (address = 0x0F) will become the default value 0x55 (Hi-Z state); The value of the Global Faults 1 Register (address = 0x11) will become 0x10 (i.e.: INVALID CLOCK).

This cycle repeats, and the speaker never outputs any sound.

Urgent, please reply as soon as possible, thank you!

  • 0
    TI__Mastermind 41405 points

    Hi,

    Do you have the MCLK pin connected to SCLK pin?  If you get a clock error, usually means a clock is missing or the FSYNC and SCLK are not phase synchronized.  

    Regards,
    Gregg Scott

  • 0 in reply to Gregg Scott
    Prodigy 10 points

    Thanks for the reply!

    The MCLK pin and SCLK pin are connected together.

    I read the datasheet and found that phase involves the settings of several related registers.

    Also, do I need to refer to 9.3.8.3.2 Impedance Phase Reference Measurement and 9.3.8.3.3 Impedance Phase Measurement for measurement?

  • 0 in reply to yaoxuefeng yaoxuefeng
    TI__Mastermind 41405 points

    Hi,

    These refer to the use of the AC Load Diagnostics.  I do not think these are related to your issue.

    I will work with your local Apps Eng.  We will respond soon.

    Regards,
    Gregg Scott

  • 0 in reply to yaoxuefeng yaoxuefeng
    Prodigy 10 points

    Hello Gregg Scott，

    1) “About The MCLK pin and SCLK pin are connected together.”

    I added the setting of this register:

    Set Bit3 of Miscellaneous Control 4 Register (address = 0x26) to 1,  according to Table 9-40. Misc Control 4 Field Descriptions：

    ”1: Inverted MCLK/BCLK phase relationship when MCLK/BCLK run at the same frequency“

    2) Regarding phase control I added the following register settings:

    a) Set the value of Miscellaneous Control 2 Register (address = 0x02) to 0x65 (or 0x66, 0x67), according to Table 9-12. Misc Control 2 Field Descriptions:

    "010: RESERVED (default, must be changed)

    100: RESERVED

    101: CH1- 0, CH2- 210, CH3- 60, CH4- 270

    110: CH1- 0, CH2- 225, CH3- 90, CH4- 315 1

    111: CH1- 0, CH2- 240, CH3- 120, CH4- 360"

    b) Set bit 5 of Miscellaneous Control 5 Register (address = 0x28) to 1, according to Table 9-41. Misc Control 5 Field Descriptions：

    “1: Supported Phase Offsets”

     

    Finally, set the Stanby pin/Mute Pin to high level, according to Table 9-12. Misc Control 2 Field Descriptions:

    “WARNING: The MSB in Miscellaneous Control 5 Register, Bit 5 must be set to '1' before the device exits STANDBY. ”

    But the result is still the same as before.

    May I ask if there are other reasons?

    Please help analyze it again, thank you！

  • 0 in reply to yaoxuefeng yaoxuefeng
    TI__Mastermind 41405 points

    The phase control is the phase control of the PWM between channels.  This would not cause a fault.  

    Can you provide the Fsync frequency, SCLK/MCLK frequency, and TDM slot size?    SCLK must be 128Fs or 256Fs in TDM mode.

    Response to your original post.

    1. If you tell the device to go into play and it stays in Hi-Z this indicates there is a fault or a load diagnostic fault. 
    2. It cannot go into Mute State, unless you tell it to go to that state.  Either with the I2C command or /Mute pin.
    3. A clock fault is autorecover, so it will recover and then fault again on a clock error.

    Regards,
    Gregg Scott

  • 0 in reply to Gregg Scott
    Prodigy 10 points

    Hello Gregg Scott,

    Fsync:   48000Hz

    SCLK/MCLK:  12.288MHz

    TDM slot size is 32 bit， 8 channels.

    SCLK/FsyncFsync

    "If you tell the device to go into play and it stays in Hi-Z this indicates there is a fault or a load diagnostic fault."

    Yes, I checked all registers, and it was the clock error (the value of Global Faults 1 Register (address = 0x11) is 0x10). There are no other faults.

    "It cannot go into Mute State, unless you tell it to go to that state.  Either with the I2C command or /Mute pin."

    I set the Mute pin to high level (unmute), because the datasheet says that low level is valid (mute).

    After setting other registers, I finally set all 4 channels to play state through Channel State Control Register (address = 0x04).

    After that, I did not use I2C commands to set this register for state switching.

    And the value of this register was also in play state when the fault occurred.

    Please continue to assist in the analysis，Thank you!

  • 0 in reply to yaoxuefeng yaoxuefeng
    TI__Mastermind 41405 points

    Thank you for sending your screenshots of the waveforms.  Is the FSync pulse at least 2 x SCLK?  From what I can see, it is wide enough.  

    Is the SCLK phase synchronized to the FSync?  I cannot tell from the screenshots.

    Gregg Scott