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TLV320ADC3140: DC offset on I2S data out when Biquad dynamic update

daisuke kawasaki
Expert 4535 points
Part Number: TLV320ADC3140

Tool/software:

Hello expert, 

We are seeing a DC offset (0x40000000) on I2S out when biquad filters are updated dynamically on the fly after the device is initilalized with a four-Channel Analog Microphone Recording set up. 

If there is any suggestion how to do it or workaround to avoid this, please let me know. 

The DC offest is not 100% repeatability, but it ocurrs < 10%. 

Thank you and best regards, 

Daisuke KAWASAKI 

  • 0
    TI__Mastermind 31605 points

    Hi Kawasaki-san,

    It is not recommended to change biquad filters on the fly. If biquad filters need to be changed, the ADC should be powered down first, update the biquad coefficients, then power up the ADC again.

    Best regards,
    Jeff McPherson

  • 0
    Prodigy 40 points

    Hi Jeff, 

    I understand that if biquad filters needs to be changed,  ADC needs to be powered down first.

    Is IN_CH_EN (0x73) the correct register to power down ADC in order to change biquad filter coefficient.

    If it is not correct, please let me know which register to control.

    Best regards,

    Yudai SHINKAI

  • 0 in reply to Yudai Shinkai
    TI__Mastermind 31605 points

    Hi Shinkai-san,

    The correct register is PWR_CFG (0x75). Bit 6 controls the ADC power up or down.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 40 points

    Hi Jeff, 

    Thank you for your reply.

    We controlled bit 6 of PWR_CFG, but it seems that the DC noise problem still occurs.

    The setting sequence is as follows.

    IN_CH_EN: Disable all channels

    PWR_CFG: Disable ADC

    Stop I2S master's BCLK and SYNC

    IN_CH_EN: Enable Ch1-4 (or Ch1-2)

    Resume I2S master's BCLK and SYNC

    Set BQ1-4 coefficients (*)

    PWR_CFG: Enable ADC

    (*)
    Set BQ in the following sequence

    Set Page to 0x02

    Set N0, N1, N2, D1, D2 to zero

    wait 5ms

    Set values ​​to N0, N1, N2, D1, D2

    Set Page to 0x00

    Please let me know which step is incorrect.

    Best Regards,

    Yudai SHINKAI

  • 0 in reply to Yudai Shinkai
    TI__Mastermind 31605 points

    Hi Shinkai-san,

    Setting the coefficients to 0 is not necessary. I would remove this step.

    Also if you don't set any biquad coefficients, is the DC problem still there?

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 40 points

    Hi Jeff,

    The DC problem do not occur if we don't set any biquad coefficients.

    The step of setting the coefficients to zero was done to prevent the filter from oscillating(not convergent) by sequentially changing the coefficients.

    The sequence below does not have any DC problems.

    I2S master's BCLK and SYNC is supplied.

    PWR_CFG: Disable ADC

    Set N0, N1, N2, D1, D2 to zero

    PWR_CFG: Enable ADC

    wait for 5ms

    PWR_CFG: Disable ADC

    Set values ​​to N0, N1, N2, D1, D2

    PWR_CFG: Enable ADC

    If there are no errors or wrong steps in this sequence, I would like to adopt it.

    Best Regards,

    Yudai SHINKAI

  • 0 in reply to Yudai Shinkai
    TI__Mastermind 31605 points

    Hi Shinkai,

    The filter should not oscillate because the ADC should not be powered on until all filter coefficients are written. However the sequence you have is okay and if you would like to adopt it, then there are no problems.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 40 points

    Hi Jeff,

    Thank you. I will use this sequence.

    Best Regards,

    Yudai SHINKAI