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Timing Questions about TLV320AIC34

Bruno Paillard
Intellectual 945 points
Other Parts Discussed in Thread: TLV320AIC34

We are starting a new project with several TLV320AIC34 on the same McBSP. In this project the relative synchronization of the various channels is important, and I have the following questions:

- If several devices (configured as slaves) are cascaded on the same McBSP bus, is it possible for them to use their individual PLLs? Can several devices work off their individual PLL and communicate synchronously on the same McBSP?

- How are the ADC and DAC samples timed relative to the TDM communication? Are the samples synchronized on the WCLK signal (i.e. all synchronous in TDM mode)? or are they each synchronized on their respective communicatino slots (i.e. staggered when in TDM mode)?

- Is the ADC and DAC sample-time synchronization fixed and reproductible relative to the communication clock, after each start? or is there some variability due to start conditions, lock of individual PLLs...etc.?

- How long do the PLLs take to lock and be stable?

- Is there a recommended startup procedure?

- I see in page 55 of the data sheet that there are "resync" bits for the ADC and DAC, that allow resynchronization of the respective module if the group-delay drifts by more than 1/4 sample. Unfortunately there is no more information than that in the data sheet. How is it possible for the group-delay to drift at all after the CODECs have started? How do these bits work?

Thanks

Bruno

 

  • 0
    TI__Mastermind 28585 points

    Hi Bruno,

     

    The sampling is based on the master clock (MCLK) and register settings. If the PLL is used the lock times will all be different so it is unlikely that the sampling will be sync'ed or even deterministic. If you don't have a clock that can be used with simple dividers, you will probably be better off to use a single PLL and have it be the master for the other CODEC's. All of the AIC34 should be set up via I2C and ready to go when the MCLK is applied. In this case, MCLK would propagate through the parts at the same time causing the sample rates to be sync'ed.

     

    The resync bits are to allow for the fact that the sample rate is actually set by MCLK and not WCLK, so this bit allows the device to resync if WCLK gets out of sync with the sample rate set by MCLK and the register settings.