TLV320AIC3111: how to generate ADC Biquad Filter Coefficients and ADC Biquad Filter Coefficients

Hi Jeff McPherson:

Thank you for your reply.

What about ADC/DAC FIR Filter Coefficients？

can you help confirm too?

Hi Jeff McPherson:

Thank you for your reply.

Is there any update about 3D PGA?

Hi Zhou,

I did not hear back but I found something that may help.

From what I can gather the 3D PGA coefficient is a measure of how intense the 3D effect is:

A value of 0 means the effect is off, a normal stereo mix.
A maximum value 0x7FFFF means that the effect is turned all the way on, creating a wide stereo image.
A minimum value of 0xFFFFF means that the Left and Right channels have been swapped. 

You can think of it as this: the more positive the coefficient, the wider the channels become. The more negative the coefficient, the closer together the channels become, first becoming a mono mix, and then swapping L and R completely. 

The EVM control software for the AIC3254 has a GUI for this.

You can drag the slider to the left or right based on how intense the effect you want. The value in the lower right is the decimal value of the coefficient required. If you convert this to hex, you can write this to the AIC3111. Because the AIC3111 and the AIC3254 have similar processing blocks, I am confident this GUI will get you the correct values.

Best regards,
Jeff McPherson

Hi Zhou,

Thank you for the correction. Are you providing I2S clocks to the device? The buffer swap won't happen unless I2S is provided.

Also the buffer swapping should be enabled before attempting to write to the coefficients if you're going to use it. 

Best regards,
Jeff McPherson

Hi Jeff McPherson:

>Are you providing I2S clocks to the device? 

---->I think yes, because I send command during playing music.

>Also the buffer swapping should be enabled before attempting to write to the coefficients if you're going to use it. 

---->Do you mean I should send command as follows? I tried but the result is same, the page 8 / register 1, bit D0 doesn't set back to 0, it will always be 1, and  page 8 / register 1, bit D1 is 0 too.

w 30 00 08
w 30 01 05

w 30 00 0C
w 30 40 7F FF

Hi Zhou,

Sorry I was not clear. I meant that the buffer swapping should be enabled before the DAC is powered on. As the data sheet mentions, while the DAC is running the coefficients are locked. If the DAC is powered on before the buffer swapping is enabled, then the turning the swapping on after the DAC is running will not work.

Best regards,
Jeff McPherson

Hi Jeff McPherson:

If so, what does this line(whith red box) mean?

I think buffer swapping is added for swap coefficients during DAC is running.

Hi Zhou,

In the paragraph above, the double buffering is turned on through page 8 register 1 bit 2. Once the double buffering is enabled, then you can swap the buffers using page 8 register 1 bit 0. It looks like your code is trying to swap the buffers before enabling the feature.

Best regards,
Jeff McPherson