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TLV320ADC3101: TLV320ADC3101

Rob Frizzell
Prodigy 50 points
Part Number: TLV320ADC3101


Tool/software:

We want the ADCs to sample the left and right channels at the exact same time so there's no phase error in the data.  A 1kHz test signal shows there's a 0.21 radian (12 degree) phase error between left and right signals.  Is it correct the right channel ADC will sample on the rising word clock and the left channel ADC will sample on the falling edge?  How do we align the left and right ADC to sample at the exact same time?

  • 0
    TI__Mastermind 27710 points

    Hi Rob,

    Assuming standard TDM timing, both channels would sample on the rising edge of BCLK. If i2s or any polarity changes, this will impact the timing format, the timing diagrams are included in the d/s.

    If there is some deviation in phase between channels, you can add phase compensation to the left or right channels in Page 0 / Register 85.

  • 0 in reply to Daveon Douglas
    Prodigy 50 points

    Thanks Daveon

    We're using I2S interface.  Are you confirming that the actual samples are taken at the rising and then falling edge of the word clock and therefore the L/R data samples have a time/phase delay between them?


    We'll take a look at the register 85 for adjustments.

  • 0 in reply to Rob Frizzell
    TI__Mastermind 27710 points

    Shown in 10.3.6.1-2 of the d/s, the left and right channel data transmit at the falling edge of the word clock.

    There is natural phase delay between channels that I have seen working with products, but to the degree of 0.0xx or less. 12degrees is large. I suggest adding the phase compensation.

    If i find any additional measures to close this gap I will update this thread this week.

    Regards,

  • +1 in reply to Daveon Douglas
    Prodigy 50 points

    We found changing the register 85 value to -128 worked or provided very little phase error.  Why -128 is not so clear as we tried calculating based on the ADC_MOD_CLK but the values calculated and register setting did not provide good results.  It'd be nice if there was just a register to set the I2S sampling to occur at the exact same time.