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PCM1753: Left/Right output channels are out of sync (time shifted)

Part Number: PCM1753

Tool/software:

I measured the output channels of the DAC with an oscilloscope, and noticed that sometimes they are not in sync; there is a slight delay or gap between left and right channels. This delay or gap is not constant, it varies slightly from one sound play to the next; i.e. if one sound is played and stopped after some seconds, the next play of the same sound may have this L/R gap. Once the gap is present, it will remain for as long as the sound is played; it varies only between play/stop cycles

I read the DAC inputs with a logic analyzer but I did not see significant differences between plays of the same sound, again I played and stopped one sound after some seconds, and repeat the steps for the same sound; the readings at the DAC input don't show any significant differences; only a few samples differ and for only in one bit, I guess this is because of the setup I have, it may introduce noise on the logic analyzer read channels.

I'm using:

* I2S 24-bit left-justified
* 16 KHz sampling freq
* 1.024 MHz bit clk freq
* 6.14 MHz sysclk freq

My questions are:

* what could cause these variations on the delay of both channels? 
* what is the clock jitter tolerance for each clock input? Could this cause channels to be out of sync?

Any ideas are welcomed Slight smile

  • Hi Luis,

    the relationship b/ween BCK and FS is

    BCK=  # of Ch  *  Ch depth * fs   ==>    so for 16KHz , 2ch & 24Bits  , BCK=48fs

    BCK should be 768KHz and you are using 1.024MHz. You should make the correction.

    Also SCK=nFs where in your case n is 384 which is fine-- but make sure your SCK is 6.144MHz

    You mentioned I2S 24-bit left justified. Pleaser refer to Figure 23. Audio Data Input Formats and see how I2S format is different from Left justify. If your data is left Justified,  check (3) Left-Justified Data Format in figure 23. But if you are sending data as  I2S see (2) I2S Data Format in figure 23. Register 20  (0h14)  sets the input format. 

    There is no value for jitter tolerance in the datasheet, but  you  read that  " The delta-sigma section of the PCM175x device is based on an 8-level amplitude quantizer and a 4th-order noise shaper.  This 8-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. TI's PLL170x family of multiclock generators is an excellent choice for providing the PCM175x system clock. " 

    The internal delay is proportional  to fs ( due to interpolation filter)  and I doubt you have any problem with the  internal delay,  as the delay should be same for both channels. I would verify the  clks as I explained above.

    Regards,

    Arash