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PCM5121: Is running PCM5121 as I2S master in hardware mode reliable

Michael Ng
Prodigy 60 points
Part Number: PCM5121

Tool/software:

Hi,

I am currently need a DAC that can provide I2S master in Hardware mode. 

I know that the PCM5121 does not support I2S master in hardware mode.

However, when my colleague configure the PCM5121 to hardware mode, he is able to decode the signals and hear the desired audio. at 48KHz. 

We would like to know why this is possible.

Can you also recommend any I2S DAC that can provide I2S master in hardware mode. We only require it to run at one sampling frequency

Thanks and Regards

Michael

  • 0
    TI__Mastermind 30861 points

    Hi Michael

    Put MODE1 = Low, MODE2 = Low so you go into  Hardwired mode.  Then in HW mode, pin 14 is MAST  which can put the device in master or slave mode :  put this pin  to  High and the IC will generated BCK/LRCK as outputs.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 60 points

    Hi Arash,

    Thanks for your reply.

    In this case, what would be the frequency of the LRCLK, i,e., the sample rate. And what mode will the I2S interface be in, L-J, R-J or I2S?

    Regards

    Michael

  • 0 in reply to Michael Ng
    TI__Mastermind 30861 points

    Hi Micheal, 

    Please refer to datasheet as you can find the information you need . pin 14 ( MAST) was in pin discription . Similarly Master mode operation  is  described in details in section 8.3.6.6 (Clock Master Mode from Audio Rate Master Clock).

    Table 83 in data sheet tells you Page 0 / Register 40  sets the format of data. 

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 60 points

    Hi Arash,

    How can I access the register if I am in hardware mode? 

    Are there any other TI products that supports I2S master in hardware mode?

  • 0 in reply to Michael Ng
    TI__Mastermind 30861 points

    Hi,

    In Hardware mode use pin FMT. If using it in software mode use register 40.

    We have PCM524x, PCM514x which are from same family, so PCM5121 that you already have is  a good choice 

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 60 points

    Hi Arash,

    When using the PCM5121 as I2S master in hardware mode, what is oscillator that we should connect to the SCK, i.e., what frequency. What is the relationship of the SCK to the I2S BCLK, i.e., what is the ratio? and how do we choose the LRCLK rate, i.e., the FS, for example, if we want to fix at 48KHz?

    Regards Michael

  • 0 in reply to Michael Ng
    TI__Mastermind 46905 points

    Hi Michael,

    Table 32 in the datasheet outlines supported SCK and FS relationships. Fs is equal to LRCLK so LRCLK = 48kHz. The BCLK is calculated with the following formula: BCLK = LRCLK * [# of Channels] * [Bit depth]

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 60 points

    Hi Jeff,

    As I am operating the DAC as I2S master in hardware mode, this means that I

    1. do not have the access to the registers in the DAC and

    2. require the DAC to generate the bit clock and LRCLK to my device.

    Please advise on how to choose between 512FS versus 256FS for 48KHz.

    i.e., When I connect a 24.576MHz OSC to the SCK pin, do I expect the FS to be 48KHz or I would expect the FS to be 96KHz or even 192KHz generating from the DAC? 

    Regards Michael

  • 0 in reply to Michael Ng
    TI__Mastermind 46905 points

    Hi Michael,

    As you mention in your first post, the device does not support configuration as an I2S master in hardware mode due to the PLL requirement. Without programming, the proper dividers will not be set and so you are not guaranteed to get the expected BCLK and LRCLK.

    Arash will be back in office Monday to look at this further. What exactly is your colleague's set up that allows him to run the device in I2S Master Hardware mode?

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 60 points

    Hi Jeff / Arash

    Below is the connections. We find that the left Justified is having left/right swap, but I2S is working.

    ,

    Regards Michael

  • 0 in reply to Michael Ng
    TI__Mastermind 30861 points

    Hi Michael,

    The schematic looks fine . With MODE1 and2 at LOW you are in HW mode and with MAST=HIGH you are in master mode,  so the device generates the LRCLK and BCK based on the external SCK and I2S should be ok.  for LJ, left channel is at LRCLK high and for I2S format, L Ch is at LRCLK =low

    I don't see any relationship in datasheet for SCK and LRCLK  (i.e., 256xFs or x 128xFs or ...) for the HW;   so I assume  it is fixed. So for the given SCK, you would get whatever ratio is set internallyand you can check this on your baord or your colleuage's board.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 60 points

    Hi Arash,

    Are there any side effects if we use it with this setup? What are the limitations that we need to observe? 

    Regards Michael

  • 0 in reply to Michael Ng
    TI__Mastermind 30861 points

    Hi Micharl,

    I am not aware of any side effect for master mode, the only limitation that I can think of  is that  PLL is not programable.

    Regards,

    Arash