• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 29 subscribers
  • Views 149 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCMD3140-Q1: Power-up state of SDOUT

Christopher Brooks
Prodigy 70 points
Part Number: PCMD3140-Q1

Tool/software:

Immediately upon providing power to AVDD and IOVDD, before providing a clock signal to GPIO1 or communicating via I2C, will SDOUT be high, low, or tri-stated?

Thanks.