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TLV320AIC3100: TLV320AIC3100 ADC Gain Control

Part Number: TLV320AIC3100


Tool/software:

I am attempting to set the gain of the analog input path for the TLV320AIC3100.

The Codec Control software specifies

w 30  0 01
w 30 2f 80

to yield a gain of 0db

My code converts "value of 0->24" to send 2 16bit words to the device (I2C)

        CinitWord[0] = 0x0001;
        CinitWord[1] = 0x2F00 | 0x80+(value*2);        // 0x2F80        
        _Sys_I2CWriteBytes(0x18,&CinitWord[0],2);    //         -------- Select Page 1 ------------                    
        _Sys_I2CWriteBytes(0x18,&CinitWord[1],2);    // ADC PGA 0x80 = 0db 0x86 = +3db   

This code does not seem to affect the gain at all for different values.

I have also tried changing the call in the initialization string from 0x2F80 to 0x2F0B (0 -> +24db) with no effect  

What else can I do to diagnose this problem?

I have confirmed that the _Sys_I2CWriteBytes(0x18, format works since the initialization sequence works.

void RunCodecInit(void)
{
WORD index;                                
WORD CinitWord[47] = {
                    0x0000,                    // * Reg 0    -------- Select Page 0         --------
                    0x0101,                    // Reg 1        s/w reset
                    0x0400,                    // * Reg 4        PLLin = MCLK pin, CodecClk = MCLK pin
                    0x0B81,                    // Reg 11        DAC NDAC div 1, power on        
                    0x0C82,                    // Reg 12        DAC MDAC div 2, power on    
                    0x0D00,                    // Reg 13        DAC DOSR MSB    
                    0x0E80,                    // Reg 14         DAC DOSR LSB
                    0x0F20,                    // Reg 15        DAC IDAC
                    0x1004,                    // Reg 16        DAC PRB Engine Interpolation    ???
                    0x1281,                    // Reg 18        ADC NDAC div 1, power on
                    0x1382,                    // Reg 19        ADC MDAC div 1, power on
                    0x1400,                    // Reg 20        ADC DOSR MSB
                    0x1580,                    // Reg 21        ADC DOSR LSB
                    0x1620,                    // Reg 22            ??
                    0x1704,                    // Reg 23            ??
                    0x1B20,                   // Reg 27         I2S,wordlength 24
                    0x4100,                    // Reg 65        DAC gain left 0db
                    0x4200,                    // Reg 66        DAC gain right 0db    
                    0x4400,                     // Reg 68          DRC disable, th and hy                                
                    0x7400,                    // Reg 116        DAC => volume control thru pin disable
                        0x0001,                    //         -------- Select Page 1 ------------
                    0x214e,                     // De-pop, Power on = 800 ms, Step time = 4 ms
                    0x1fc2,                     // HPL and HPR powered up    // ******************************************
                    0x2344,                    // LDAC routed to HPL, Class D; RDAC routed to HPR
                    0x280E,                    // HPL unmute and gain 1db,
                    0x290E,                    // HPR unmute and gain 1db
                    0x2400,                    // No attenuation on HP
                    0x2500,                    // ******************************************
                    0x2600,                    // Class D Atten = 0         
                    0x2A04,                 // Class D             04 -> 6db        1C ->+24db gain // ******************************************
                    0x2e0b,                    // MIC BIAS = AVDD
                    0x2F80,                    // ADC PGA 0x80 = 0db 0x0B = +24db     0x98 - +12db   // ******************************************                    
                    0x3040,                    // MICPGA P = MIC 10k
                    0x3140,                    // MICPGA M - CM 10k
                        0x0000,                 //         -------- page 0 is selected         --------
                    0x3c0b,                 // select DAC DSP mode 11 & enable adaptive filter
                    0x0008,                 //
                    0x0104,                 //
                        0x0000,                 //
                    0x3fd6,                    // POWERUP DAC left and right channels (soft step disable)
                    0x4000,                 // UNMUTE DAC left and right channels
                    0x5180,                    // POWERUP ADC channel
                    0x5200,                    // UNMUTE ADC channel
                        0x0001,                 //         --------  page 1 is selected         --------
                    0x2a1c,                 // Unmute Class-D Left
                    0x2b1c,                 // Unmute Class-D Right
                    0x20c6,                    // Power-up Class-D drivers
                    };
                                                                
_Sys_I2CInit(0,0,12,11);    // delay , port , sda , scl
for (index=0;index<47;index++)
    _Sys_I2CWriteBytes(0x18,&CinitWord[index],2);
DebugPlace = 1;    
}