• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 30 subscribers
  • Views 97 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCM4201EVM: A doubt about schematic

HD
Prodigy 180 points
Part Number: PCM4201EVM

Tool/software:

Hi,

I need support about the PCM4201EVM schematic.

My doubt is related to U4 (SN74ALVC245PW) and how the SDOUT output signal is managed because it is an output and it is connected to B5... but in Slave mode (S/M=1) the direction is from A to B. Is It a mistake? How does it works for the two configuration Master/Slave?

Thanks for your support.

  • 0
    TI__Mastermind 19480 points

    Hi,

    U4 is a tri-state buffer to control the output drive of the pin in low power conditions. SDOUT is directed from the IC to the audio serial port J3 where the user can monitor the digital output. 

    Master and slave mode do not impact DOUT, only the master of BCLK and FSYNC.

  • 0 in reply to Daveon Douglas
    Prodigy 180 points

    Hi,

    ok but Master/Slave impact on direction of U4 that is bidirectional. In Slave mode (S/M=1) the direction is from A to B so A is an input and B an output... and SDOUT is connected to B5 that is an output. It seems a conflict for monitoring SDOUT from J3. I don't know if it is clear what I say.

  • 0 in reply to HD
    TI__Mastermind 19480 points

    Hi HD,

    I understand your point and based on the schematic it it not clear how a provision is made for SDOUT to flow from B5 to A5 in slave mode. However, I have used PCM420x EVM in both slave and master mode, I have had no issue receiving SDOUT on header J3.