TLV320AIC3109-Q1: About the meaning of fs(ref)

Takahiro Okutsu

Part Number: TLV320AIC3109-Q1

Tool/software:

Hi, About TLV320AIC3109, We are planning our system with fs=8kHz, MCLK=2.56MHz with target mode. I don't understand about the meaning of fs(ref). Is it for bring high accuracy on the PLL by selecting frequency of 44.1kHz group, or 48kHz group? For example, setting of fs(ref)=40kHz(it's not a general sampling freqency) could bring high accuracy,too? Please teach me the role of fs(ref).Best regards, Takahiro Okutsu.

30 days ago

0 Daveon Douglas 29 days ago

TI__Mastermind 18750 points

Hi,

Our codec expert is out of office, they will be able to get to your question Monday.

0 Jeff McPherson 27 days ago in reply to Daveon Douglas

TI__Mastermind 32955 points

Hi Okutsu-san,

fs(ref) is the internal clock rate used by the device. This controls things such as the modulation frequency. fs(ref) = 48k or 44.1k will give the highest performance, so for your case I would use fs(ref) = 48k (8kHz * 6 = 48kHz). I would focus on this picture to understand the meaning:

I find it easier to work backwards from the bottom. With NCODEC = 6, fs(ref) = WCLK * NCODEC = 48kHz. Then CODEC_CLK = 256 * fs(ref) = 12.288MHz. Now you can solve for either the PLL output or the CLKDIV_OUT based on your available MCLK or BCLK.

Best regards,
Jeff McPherson

0 Takahiro Okutsu 26 days ago in reply to Jeff McPherson

Prodigy 70 points

Hi,Jeff-san, Thank you for your advice that we should to set fs(ref)=48kHz and NCODEC as 6.I could understand that is the best ratio as the internal clock(for FIR Filter coefficients & etc.), and I will recommend it to our customer, they are studying and would dicide them. Best regards,Takahiro Okutsu

0 Takahiro Okutsu 11 days ago in reply to Takahiro Okutsu

Prodigy 70 points

Hi Jeff-san.This question may be a duplicate of another thread, so please forgive me. I had known that under fs=8kHz, the Anti-Aliasing Filter's cut-off frequency is about 2kHz by our experiment with DSP & 3109EVM. And our needs is the level is almost unity at 3.5kHz(SineWave).Is it possible by any other setting operations? Now I attach our register setting in .txt file. Best regards,Takahiro Okutsu.

AIC3109_RegSetting.txt

AIC3109_rset( 0, 0x00 );//Set PAGE_0
AIC3109_rset( 1, 0x80 );//Reset CODEC
AIC3109_rset( 1, 0x00 );//Clear Reset

//################ MCLK Selection ##################
	AIC3109_rset( 2, 0xAA );//ADC:48kHz(fsREF)/6=8kHz, DAC:48kHz(fsREF)/6=8kHz
//################ MCLK Selection ##################

AIC3109_rset( 3, 0x91 );//PLL Enable, PLL_Q(NoUse)=0010, Pll_P=1

//################ MCLK Selection ##################
	AIC3109_rset( 4, 0x30 );//PLL_J=001000(48), bit1=bit0=0 fs(REF)=256k x K(=J.D) x R / 2048 x P <- K=48, R=8, P=1, then fs(REF)=48k
//################ MCLK Selection ##################

AIC3109_rset( 5, 0x00 );//PLL_D=00000000(K=J.D Fraction.0.9999)
AIC3109_rset( 6, 0x00 );//PLL_D=000000(K=J.D Fraction 0.9999), bit1=bit0=00

//################ MCLK Selection ##################
	AIC3109_rset( 7, 0x08 );//bit7=0-> fsREF=48kHz, DAC_Dual_Rate_Ctrl=Disable, DAC_DATA_Path_Ctrl_A=Disable, DAC_DATA_Path_Ctrl_B=01(LeftCH), bit2�`bit0=0
//################ MCLK Selection ##################

AIC3109_rset( 8, 0x00 );//BCLKtoIn(=SlaveMode), WCKtoIn(=SlaveMode), SO<-Drv_NoChangeToHiImp, BCLK/WCLK_Drv_NoChangeToHiImp, bit3-bi0=0

AIC3109_rset( 9, 0x00 );//bit7-bit6=00(=I2S_Mode), bit5-bit4=00(=16bit), BCLK_Rate=0, DAC_ReSync=0, ADC_ReSync=0, Re_SyncMode=0
AIC3109_rset( 10, 0x00 );//I2S_SlotOFFSET=0

AIC3109_rset( 11, 0x08 );//bit7->ADC_OVF_FLG, bit6=0(reserved), bit5->DAC_OVF_FLG, bit4=(reserved), bit3-0:PLL_R=1000(=8)

//20241025	AIC3109_rset( 12, 0x10 );//ADC_HPF->100Hz, 
AIC3109_rset( 12, 0x00 );//ADC_HPF->Disable, 

AIC3109_rset( 15, 0x00 );//AGC_PGA_MUTE:OFF, 
AIC3109_rset( 16, 0x00 );//PGA_AUX Mute:OFF, 

AIC3109_rset( 19, 0x84 );//MIC/LINE_1_Input_Lev_CTRL for ADC PGA=Differentioal_Mode, ADC_ch_PWR_UP 

AIC3109_rset( 21, 0x08 );//MIC/LINE_2_Input_Lev_CTRL for ADC PGA, 

AIC3109_rset( 37, 0x80 );//bit7:DAC Power CTRL, 

AIC3109_rset( 42, 0x64 );//DAC_DrvPowerOn_Delay, Drv_RampUp_StepTiming_CTRL, 
AIC3109_rset( 43, 0x00 );//DAC_DigitalMute:OFF, DAC_DigVol_CTRL:0x00(0dB), 

AIC3109_rset( 82, 0x80 );//bit7:DAC_1_Output_Routing_CTRL, DAC_1_to_LEFT_LOP/M Anlg_VOL_CTRL->0dB, 

AIC3109_rset( 86, 0x0D );//LEFT_LOP/M_OutLevCTRL LEFT_LOP/M_Mute:OFF, 

//################ MCLK Selection ##################
	AIC3109_rset( 102, 0xA0 );//CLKDIV_IN->BCLK, //ADC -> DAC OK!
//################ MCLK Selection ##################

0 Jeff McPherson 10 days ago in reply to Takahiro Okutsu

TI__Mastermind 32955 points

Hi Okutsu-san,

There is no true anti-aliasing filter in this device. Delta-sigma ADCs like the ones we use in TI Audio oversample the data and then use a decimation filter to remove the out of band content. The decimation filter for the ADC has a cut off of 0.45fs = 3.6kHz for 8k sample rate. I am surprised to hear you are finding the cut off to be 2kHz.

Could you give some more detail about how you are testing the frequency response and deriving the 2k limit?

Thank you,
Jeff McPherson

0 Takahiro Okutsu 10 days ago in reply to Jeff McPherson

Prodigy 70 points

Hi,Jeff-san. Thank you for new information about ADC's cutoff=3.6kHz. Then it seems to be wrong in my experiments.As I raise the freq higher, then 3.5kHz Out becomes correctly(ex.setting to fs=32kHz). Although I know sync would be collapse, as make the value of Reg2(ADC/DAC SampleRateSelects) smaller, the 3.5kHz_wave_Level returns(increases). Here I attach a document, Reg. settings, and pictures of my experiments.If you guess the causes of the difference of cutoff freq.,please point out & let me know.Best regards,Takahito Okutsu.T_Okutsu_Rxp.zip

0 Daveon Douglas 9 days ago in reply to Takahiro Okutsu

TI__Mastermind 18750 points

Jeff is out of office and will continue thread Monday

0 Takahiro Okutsu 6 days ago in reply to Daveon Douglas

Prodigy 70 points

Hi,Jeff-san.I tried to read check all registers page0 & page1 in AIC3109.And i find that values of Register65 of page1 is "0x7F",and it's different from default value "0x39"on the data sheet.Then I tried to write it to "0x39",but it returns "0x7F" as forcefully.Is it correct phenomenon? The other registers seems to be working correctly.(All coef. of digital filters are just the default values).Problem of cutoff seems to not be 0.45*fs=3.6kHz,but 2kHz,is no change(not resolved)yet. Best regards,Takahiro Okutsu.

0 Jeff McPherson 5 days ago in reply to Takahiro Okutsu

TI__Mastermind 32955 points

Hi Okutsu-san,

Register 65 is part of the high pass filter coefficients. If you try to write only a single register, then the result will not take effect. You have to re-write all coefficients sequentially for the filter in order to see the change.

I am catching up from some international travel, but I can use the settings you provided and experiment myself to see if I can recreate the problem or if it is a test set up problem.

Best regards,
Jeff McPherson

0 Takahiro Okutsu 5 days ago in reply to Jeff McPherson

Prodigy 70 points

Hi,Jeff-san.Thank you very much for your reply.The updated Reg. setting is as attempt "RegSet_Chk_AIC3109.txt". (Many of codes appended to check values of All Regsters.)If you can, Please point out any mistake in my settings.Or should I suspect my hardwares or others? I cannot understand why the cutoff freq.to be about at 2kHz,(not 3.6kHz at fs=8kHz as your information. Best Regards.Takahiro Okutsu.

RegSet_Chk_AIC3109.txt

//AIC3109_rset( 0x1E, 0x2F );//Reset AIC3109 20241021
AIC3109_rset( 0, 0x00 );//Set PAGE_0
AIC3109_rset( 1, 0x80 );//Reset CODEC
AIC3109_rset( 1, 0x00 );//Clear Reset


//%%% fs�ύX //################ MCLK Selection ##################
#if (PLL_98M ==1)
//20241119	AIC3109_rset( 2, 0xAA );//ADC:48kHz(fsREF)/6=8kHz, DAC:48kHz(fsREF)/6=8kHz
	AIC3109_rset( 2, 0x00 );//ADC:48kHz(fsREF)/1=48kHz, DAC:48kHz(fsREF)/1=48kHz
#elif (PLL_65M ==1)
//20241119	AIC3109_rset( 2, 0x88 );//ADC:40kHz(fsREF)/5=8kHz, DAC:40kHz(fsREF)/5=8kHz
	AIC3109_rset( 2, 0xAA );//ADC:48kHz(fsREF)/6=8kHz, DAC:48kHz(fsREF)/6=8kHz
//20241120_Test	AIC3109_rset( 2, 0x44 );//ADC:48kHz(fsREF)/3=16kHz, DAC:48kHz(fsREF)/3=16kHz
//20241120_Test	AIC3109_rset( 2, 0x33 );//ADC:48kHz(fsREF)/1.5=32kHz, DAC:48kHz(fsREF)/1.5=32kHz
#endif

//20241122_test
//20241124code_AIC3109 = AIC3109_rget( 0x02 );//Read Reg. = 3

//################ MCLK Selection ##################

AIC3109_rset( 3, 0x91 );//PLL Enable, PLL_Q(NoUse)=0010, Pll P=1

//%%% fs�ύX //################ MCLK Selection ##################
#if (PLL_98M ==1)
//20231119	AIC3109_rset( 4, 0xC0 );//PLL_J=110000(48), bit1=bit0=0
	AIC3109_rset( 4, 0x20 );//PLL_J=001000(32), bit1=bit0=0
#elif (PLL_65M ==1)

	AIC3109_rset( 4, 0x30 );//PLL_J=110000(48), bit1=bit0=0 fs(REF)=256k x K(=J.D) x R / 2048 x P �� K=48, R=8, P=1,�䂦��fs(REF)=48k
//20241121_Test	AIC3109_rset( 4, 0x18 );//PLL_J=011000(24), bit1=bit0=0 fs(REF)=512k x K(=J.D) x R / 2048 x P �� K=24, R=8, P=1,�䂦��fs(REF)=48k
//20241120_Test	AIC3109_rset( 4, 0x0C );//PLL_J=001100(12), bit1=bit0=0 fs(REF)=1024k x K(=J.D) x R / 2048 x P �� K=12, R=8, P=1,�䂦��fs(REF)=48k
#endif
//################ MCLK Selection ##################

AIC3109_rset( 5, 0x00 );//PLL_D=00000000(K=J.D�̏����_�ȉ���.0.9999�����)
AIC3109_rset( 6, 0x00 );//PLL_D=000000(K=J.D�̏����_�ȉ���.0.9999�����), bit1=bit0=00

//################ MCLK Selection ##################
AIC3109_rset( 7, 0x08 );//bit7=0-> fsREF=48kHz, DAC_Dual_Rate_Ctrl=Disable, DAC_DATA_Path_Ctrl_A=Disable, DAC_DATA_Path_Ctrl_B=01(LeftCH), bit2�`bit0=0
//20241118	AIC3109_rset( 7, 0x88 );//bit7=1-> fsREF=44.1kHz, DAC_Dual_Rate_Ctrl=Disable, DAC_DATA_Path_Ctrl_A=Disable, DAC_DATA_Path_Ctrl_B=01(LeftCH), bit2�`bit0=0
//################ MCLK Selection ##################

AIC3109_rset( 8, 0x00 );//BCLKtoIn(=SlaveMode), WCKtoIn(=SlaveMode), SO<-Drv_NoChangeToHiImp, BCLK/WCLK_Drv_NoChangeToHiImp, bit3-bi0=0

AIC3109_rset( 9, 0x00 );//bit7-bit6=00(=I2S_Mode), bit5-bit4=00(=16bit), BCLK_Rate=0, DAC_ReSync=0, ADC_ReSync=0, Re_SyncMode=0
AIC3109_rset( 10, 0x00 );//I2S_SlotOFFSET=0

#if (PLL_98M ==1)
AIC3109_rset( 11, 0x02 );//bit7->ADC_OVF_FLG, bit6=0(reserved), bit5->DAC_OVF_FLG, bit4=(reserved), bit3-0:PLL_R=0010(=2)
#elif (PLL_65M ==1)
AIC3109_rset( 11, 0x08 );//bit7->ADC_OVF_FLG, bit6=0(reserved), bit5->DAC_OVF_FLG, bit4=(reserved), bit3-0:PLL_R=1000(=8)
#endif

//20241025	AIC3109_rset( 12, 0x10 );//ADC_HPF->100Hz, 
AIC3109_rset( 12, 0x00 );//ADC_HPF->Disable, 

AIC3109_rset( 15, 0x00 );//AGC_PGA_MUTE:OFF, 
AIC3109_rset( 16, 0x00 );//PGA_AUX Mute:OFF, 

AIC3109_rset( 19, 0x84 );//MIC/LINE_1_Input_Lev_CTRL for ADC PGA=Differentioal_Mode, ADC_ch_PWR_UP 

AIC3109_rset( 21, 0x08 );//MIC/LINE_2_Input_Lev_CTRL for ADC PGA, 

AIC3109_rset( 37, 0x80 );//bit7:DAC Power CTRL, 

AIC3109_rset( 42, 0x64 );//DAC_DrvPowerOn_Delay, Drv_RampUp_StepTiming_CTRL, 
//20241024	AIC3109_rset( 43, 0x08 );//DAC_DigitalMute:OFF, DAC_DigVol_CTRL:0x08(-4dB?), 
AIC3109_rset( 43, 0x00 );//DAC_DigitalMute:OFF, DAC_DigVol_CTRL:0x00(0dB), 

//################ PGA_AUX_Route ##################
//20241101_Test AIC3109_rset( 81, 0x94 );//bit7:PGA_AUX_Route_ON, PGA_to_LEFT_LOP_VOL_CTRL->-10dB, 
//20241118 AIC3109_rset( 81, 0x80 );//bit7:PGA_AUX_Route_ON, PGA_to_LEFT_LOP_VOL_CTRL->0dB, 
//################ PGA_AUX_Route ##################

AIC3109_rset( 82, 0x80 );//bit7:DAC_1_Output_Routing_CTRL, DAC_1_to_LEFT_LOP/M Anlg_VOL_CTRL->0dB, 

AIC3109_rset( 86, 0x0D );//LEFT_LOP/M_OutLevCTRL LEFT_LOP/M_Mute:OFF, 

//################ MCLK Selection ##################
#if (PLL_98M ==1)
	AIC3109_rset( 102, 0x00 );//CLKDIV_IN->MCLK, PLL_CLKIN->MCLK
#elif (PLL_65M ==1)
	AIC3109_rset( 102, 0xA0 );//CLKDIV_IN->BCLK, //ADC -> DAC OK!
#endif
//################ MCLK Selection ##################

/*20241125*/
//Settled Reg.
code_AIC3109 = AIC3109_rget( 2 );//Read Reg. = 0xAA
code_AIC3109 = AIC3109_rget( 3 );//Read Reg. = 0x91
code_AIC3109 = AIC3109_rget( 4 );//Read Reg. = 0x30
code_AIC3109 = AIC3109_rget( 5 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 6 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 7 );//Read Reg. = 0x08
code_AIC3109 = AIC3109_rget( 8 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 9 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 10 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 11 );//Read Reg. = 0x08
code_AIC3109 = AIC3109_rget( 12 );//Read Reg. = 0x00 ADC_HPF(bit7,bit6), DAC_De-Emph_Filter(bit3,bit2)
code_AIC3109 = AIC3109_rget( 15 );//Read Reg. = 0x00 // ADC_MUTE, ADCPGA Gain
code_AIC3109 = AIC3109_rget( 16 );//Read Reg. = 0x00 // PGA_AUX, ADCPGA Gain
code_AIC3109 = AIC3109_rget( 19 );//Read Reg. = 0x84 // Mic1P/Line1P Input1 Lev Control
code_AIC3109 = AIC3109_rget( 21 );//Read Reg. = 0x08 // Mic2P/Line2P Input1 Lev Control
code_AIC3109 = AIC3109_rget( 37 );//Read Reg. = 0x80 // DAC PWR CTRL, ADC PWR STT, Sig.Det STT, AGC Saturation STT.
code_AIC3109 = AIC3109_rget( 42 );//Read Reg. = 0x64
code_AIC3109 = AIC3109_rget( 43 );//Read Reg. = 0x00 //DAC Dig.Volume CTRL
code_AIC3109 = AIC3109_rget( 82 );//Read Reg. = 0x80 //DAC1 to Left_LOP/M Ana Volume CTRL
code_AIC3109 = AIC3109_rget( 86 );//Read Reg. = 0x08 //Left_LOP/M Output Lev CTRL
code_AIC3109 = AIC3109_rget( 102 );//Read Reg. = 0xA0


//Non settled Reg.
code_AIC3109 = AIC3109_rget( 13 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 14 );//Read Reg. = 0x00
// Page0�ɂ͂Ȃ��Icode_AIC3109 = AIC3109_rget( 17 );//Read Reg. = 0x00
// Page0�ɂ͂Ȃ��Icode_AIC3109 = AIC3109_rget( 18 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 20 );//Read Reg. = 0x78
code_AIC3109 = AIC3109_rget( 22 );//Read Reg. = 0x78
// Page0�ɂ͂Ȃ��Icode_AIC3109 = AIC3109_rget( 23 );//Read Reg. = 0x0
// Page0�ɂ͂Ȃ��Icode_AIC3109 = AIC3109_rget( 24 );//Read Reg. = 0x0
code_AIC3109 = AIC3109_rget( 25 );//Read Reg. = 0x06
code_AIC3109 = AIC3109_rget( 26 );//Read Reg. = 0x00 // AGC Enable
code_AIC3109 = AIC3109_rget( 27 );//Read Reg. = 0xFE // AGC Max Gain Allowed
code_AIC3109 = AIC3109_rget( 28 );//Read Reg. = 0x00 //Noise Gate, AGC Clip Step Control
code_AIC3109 = AIC3109_rget( 29 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 30 );//Read Reg. = 0xFE
code_AIC3109 = AIC3109_rget( 31 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 32 );//Read Reg. = 0x80//Ch Gain Applied by AGC Algo.
code_AIC3109 = AIC3109_rget( 33 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 34 );//Read Reg. = 0x00// AGC Noise Detect Debounce CTRL
code_AIC3109 = AIC3109_rget( 35 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 36 );//Read Reg. = 0x00

code_AIC3109 = AIC3109_rget( 38 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 39 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 40 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 41 );//Read Reg. = 0x00

code_AIC3109 = AIC3109_rget( 44 );//Read Reg. = 0x80
code_AIC3109 = AIC3109_rget( 45 );//Read Reg. = 0x00

code_AIC3109 = AIC3109_rget( 51 );//Read Reg. = 0x04
code_AIC3109 = AIC3109_rget( 52 );//Read Reg. = 0x00

code_AIC3109 = AIC3109_rget( 58 );//Read Reg. = 0x04
code_AIC3109 = AIC3109_rget( 59 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 60 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 61 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 62 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 63 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 64 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 65 );//Read Reg. = 0x04
code_AIC3109 = AIC3109_rget( 66 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 67 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 68 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 69 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 70 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 71 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 72 );//Read Reg. = 0x04
code_AIC3109 = AIC3109_rget( 73 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 74 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 75 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 76 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 77 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 78 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 79 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 80 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 81 );//Read Reg. = 0x00 //PGA to Left LOP/M Ana Volume CTRL

code_AIC3109 = AIC3109_rget( 83 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 84 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 85 );//Read Reg. = 0x00

code_AIC3109 = AIC3109_rget( 87 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 88 );//Read Reg. = 0x00 //DAC1_Out Routing CTRL
code_AIC3109 = AIC3109_rget( 89 );//Read Reg. = 0x00 //DAC1 to Right_LOP/M Ana Volume CTRL
code_AIC3109 = AIC3109_rget( 90 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 91 );//Read Reg. = 0x00 //PGA_AUX to Right_LOP/M Ana Volume CTRL
code_AIC3109 = AIC3109_rget( 92 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 93 );//Read Reg. = 0x00 //Right_LOP/M Output Lev CTRL
code_AIC3109 = AIC3109_rget( 94 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 95 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 96 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 97 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 98 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 99 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 100 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 101 );//Read Reg. = 0x00

code_AIC3109 = AIC3109_rget( 103 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 104 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 105 );//Read Reg. = 0x00

code_AIC3109 = AIC3109_rget( 107 );//Read Reg. = 0x00  ADC_DigOutput_Progmable Filter_Path_Sel
code_AIC3109 = AIC3109_rget( 108 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 109 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 110 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 111 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 112 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 113 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 114 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 115 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 116 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 117 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 118 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 119 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 120 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 121 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 122 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 123 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 124 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 125 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 126 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 127 );//Read Reg. = 0x00


AIC3109_rset( 0, 0x01 );//Set PAGE_1

AIC3109_rset( 65, 0x39 );//20241125 Set Coef to Default Value!
code_AIC3109 = AIC3109_rget( 65 );//Read Reg. = should to be 0x39!


code_AIC3109 = AIC3109_rget( 0 );//Read Reg. = 0x01

code_AIC3109 = AIC3109_rget( 1 );//Read Reg. = 0x6B//Audio Eff Filter N0 Coef_MSB
code_AIC3109 = AIC3109_rget( 2 );//Read Reg. = 0xE3//Audio Eff Filter N0 Coef_LSB
code_AIC3109 = AIC3109_rget( 3 );//Read Reg. = 0x96//Audio Eff Filter N1 Coef_MSB
code_AIC3109 = AIC3109_rget( 4 );//Read Reg. = 0x66//Audio Eff Filter N1 Coef_LSB
code_AIC3109 = AIC3109_rget( 5 );//Read Reg. = 0x67//Audio Eff Filter N2 Coef_MSB
code_AIC3109 = AIC3109_rget( 6 );//Read Reg. = 0x5D//Audio Eff Filter N2 Coef_LSB
code_AIC3109 = AIC3109_rget( 7 );//Read Reg. = 0x6B//  Eff Filter Coef Under here��
code_AIC3109 = AIC3109_rget( 8 );//Read Reg. = 0xE3
code_AIC3109 = AIC3109_rget( 9 );//Read Reg. = 0x96
code_AIC3109 = AIC3109_rget( 10 );//Read Reg. = 0x66
code_AIC3109 = AIC3109_rget( 11 );//Read Reg. = 0x67
code_AIC3109 = AIC3109_rget( 12 );//Read Reg. = 0x5D
code_AIC3109 = AIC3109_rget( 13 );//Read Reg. = 0x7D
code_AIC3109 = AIC3109_rget( 14 );//Read Reg. = 0x83
code_AIC3109 = AIC3109_rget( 15 );//Read Reg. = 0x84
code_AIC3109 = AIC3109_rget( 16 );//Read Reg. = 0xEE
code_AIC3109 = AIC3109_rget( 17 );//Read Reg. = 0x7D
code_AIC3109 = AIC3109_rget( 18 );//Read Reg. = 0x83
code_AIC3109 = AIC3109_rget( 19 );//Read Reg. = 0x84
code_AIC3109 = AIC3109_rget( 20 );//Read Reg. = 0xEE
code_AIC3109 = AIC3109_rget( 21 );//Read Reg. = 0x39
code_AIC3109 = AIC3109_rget( 22 );//Read Reg. = 0x55
code_AIC3109 = AIC3109_rget( 23 );//Read Reg. = 0xF3
code_AIC3109 = AIC3109_rget( 24 );//Read Reg. = 0x2D//  Eff Filter Coef Above here��
code_AIC3109 = AIC3109_rget( 25 );//Read Reg. = 0x53//Audio Eff Filter N0 Coef_MSB
code_AIC3109 = AIC3109_rget( 26 );//Read Reg. = 0x7E//Audio Eff Filter N0 Coef_LSB
code_AIC3109 = AIC3109_rget( 27 );//Read Reg. = 0x6B//  Eff Filter Coef Under here��
code_AIC3109 = AIC3109_rget( 28 );//Read Reg. = 0xE3
code_AIC3109 = AIC3109_rget( 29 );//Read Reg. = 0x96
code_AIC3109 = AIC3109_rget( 30 );//Read Reg. = 0x66
code_AIC3109 = AIC3109_rget( 31 );//Read Reg. = 0x67
code_AIC3109 = AIC3109_rget( 32 );//Read Reg. = 0x5D
code_AIC3109 = AIC3109_rget( 33 );//Read Reg. = 0x6B
code_AIC3109 = AIC3109_rget( 34 );//Read Reg. = 0xE3
code_AIC3109 = AIC3109_rget( 35 );//Read Reg. = 0x96
code_AIC3109 = AIC3109_rget( 36 );//Read Reg. = 0x66
code_AIC3109 = AIC3109_rget( 37 );//Read Reg. = 0x67
code_AIC3109 = AIC3109_rget( 38 );//Read Reg. = 0x5D
code_AIC3109 = AIC3109_rget( 39 );//Read Reg. = 0x7D
code_AIC3109 = AIC3109_rget( 40 );//Read Reg. = 0x83
code_AIC3109 = AIC3109_rget( 41 );//Read Reg. = 0x84
code_AIC3109 = AIC3109_rget( 42 );//Read Reg. = 0xEE
code_AIC3109 = AIC3109_rget( 43 );//Read Reg. = 0x7D
code_AIC3109 = AIC3109_rget( 44 );//Read Reg. = 0x83
code_AIC3109 = AIC3109_rget( 45 );//Read Reg. = 0x84
code_AIC3109 = AIC3109_rget( 46 );//Read Reg. = 0xEE
code_AIC3109 = AIC3109_rget( 47 );//Read Reg. = 0x39
code_AIC3109 = AIC3109_rget( 48 );//Read Reg. = 0x55
code_AIC3109 = AIC3109_rget( 49 );//Read Reg. = 0xF3
code_AIC3109 = AIC3109_rget( 50 );//Read Reg. = 0x2D
code_AIC3109 = AIC3109_rget( 51 );//Read Reg. = 0x53
code_AIC3109 = AIC3109_rget( 52 );//Read Reg. = 0x7E
code_AIC3109 = AIC3109_rget( 53 );//Read Reg. = 0x7F
code_AIC3109 = AIC3109_rget( 54 );//Read Reg. = 0xFF
code_AIC3109 = AIC3109_rget( 55 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 56 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 57 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 58 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 59 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 60 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 61 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 62 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 63 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 64 );//Read Reg. = 0x00//  Eff Filter Coef Above here��
code_AIC3109 = AIC3109_rget( 65 );//Read Reg. = 0x39//ADC HPF N0 Coef_MSB // �������v�`�F�b�N�I0x39�Ə����Ă�0x7F�ɂȂ��Ă��܂��I
code_AIC3109 = AIC3109_rget( 66 );//Read Reg. = 0xEA//ADC HPF N0 Coef_LSB
code_AIC3109 = AIC3109_rget( 67 );//Read Reg. = 0x80//   :
code_AIC3109 = AIC3109_rget( 68 );//Read Reg. = 0x16//   :
code_AIC3109 = AIC3109_rget( 69 );//Read Reg. = 0x7F//ADC HPF N0 Coef_MSB
code_AIC3109 = AIC3109_rget( 70 );//Read Reg. = 0xD5//ADC HPF N0 Coef_LSB
code_AIC3109 = AIC3109_rget( 71 );//Read Reg. = 0x7F//Reserved from here��
code_AIC3109 = AIC3109_rget( 72 );//Read Reg. = 0xEA
code_AIC3109 = AIC3109_rget( 73 );//Read Reg. = 0x80
code_AIC3109 = AIC3109_rget( 74 );//Read Reg. = 0x16
code_AIC3109 = AIC3109_rget( 75 );//Read Reg. = 0x7F
code_AIC3109 = AIC3109_rget( 76 );//Read Reg. = 0xD5
code_AIC3109 = AIC3109_rget( 77 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 78 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 80 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 81 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 82 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 83 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 84 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 85 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 86 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 87 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 88 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 89 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 90 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 91 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 92 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 93 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 94 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 95 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 96 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 97 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 98 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 99 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 100 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 101 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 102 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 103 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 104 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 105 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 106 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 107 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 108 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 109 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 110 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 111 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 112 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 113 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 114 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 115 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 116 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 117 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 118 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 119 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 120 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 121 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 122 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 123 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 124 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 125 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 126 );//Read Reg. = 0x00
code_AIC3109 = AIC3109_rget( 127 );//Read Reg. = 0x00

0 Takahiro Okutsu 5 days ago in reply to Takahiro Okutsu

Prodigy 70 points

Hi Jeff-san.I missed to write that "#elif (PLL_65M ==1)" <- to select fs=8kHz is selected in the last message.Best Regards,Takahiro Okutsu.

0 Jeff McPherson 4 days ago in reply to Takahiro Okutsu

TI__Mastermind 32955 points

Hi Okustsu-san,

Am I interpreting your code correctly as AIC3109_rset( [decimal register address], [hex register value] )?

Thank you,
Jeff McPherson

0 Takahiro Okutsu 4 days ago in reply to Jeff McPherson

Prodigy 70 points

Hi,Jeff-san.AIC3109_rset(Decimal Reg Address, Hex data value) means just as you say.I'm sorry for the lack of my explanation.Then I'm trying to pass the signals as ADC out to Digital filter directly(without sending to DSP=I2S) using "SW-D1" as BLOCK Dia.in page16/122 of the data sheet.Can we control SW-D1 by bit3 of Register 107?Best regards.Takahiro Okutsu.

0 Jeff McPherson 3 days ago in reply to Takahiro Okutsu

TI__Mastermind 32955 points

Hi Okutsu-san,

You are correct that you can control the switch with that bit, however you should only use the switch if you want to enable record-only mode. This means that you can pass the ADC out to the digital filters and then out through I2S, but you will not be able to playback the audio from the DAC. It is not a pass-through or loopback type feature. See the snippet from the data sheet below:

In applications where record-only is selected and the DAC is powered down, the playback path signal processing blocks can be used in the ADC record path. These filtering blocks can support high-pass, low-pass, band-pass, or notch filtering. In this mode, the record-only path has switches SW-D1 and SW-D2 closed, and reroutes the ADC output data through the digital signal processing blocks. Because the DAC digital signal processing blocks are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digital processing and are located in registers 1–26, page 1. This record-only mode is enabled by powering down the DAC by writing to bit 7 in register 37, page 0 (where bit 7 = 0). Next, enable the digital filter pathway for the ADC by writing a 1 to bit 3 in register 107, page 0. (This pathway is only enabled if the DAC is powered down.) Figure 27 shows the record-only path.

Best regards,
Jeff McPherson

0 Takahiro Okutsu 3 days ago in reply to Jeff McPherson

Prodigy 70 points

Hi,Jeff-san.Thank you for the information about SW-D1.And I'm sorry for the continuous questions.I'm trying to 2kHz sine wave into ADC-DAC without DSP(by only this codec) to check if the cutoff occurres at 2kHz or not. "The cutoff of 2kHz@fs=8kHz probrem" is not resolved yet.Please continue to point out any wrong operation in my settings & other.Best regards,Takahiro Okutsu.

0 Jeff McPherson 2 days ago in reply to Takahiro Okutsu

TI__Mastermind 32955 points

Hi,

Today is a holiday for our team in the U.S. We will follow up when our team returns on Friday.

Thank you for your patience,
Jeff McPherson

Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

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TLV320AIC3109-Q1: About the meaning of fs(ref)