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TAS6584-Q1: Latched register bits are not cleared I2C Sequential Read

Part Number: TAS6584-Q1


Tool/software:

To reduce the I2C overhead, we try to use the I2C Sequential Read to read multiple registers. However, when reading latched registers, for example from "RTLDG OL SL Fault Mem Register "(Address = 0x8B) to "Ch OC DC Fault Mem Register" (Address = 0x8E), it seems that the latched bits within those registers are not getting reset. Is this the intended behavior? As a workaround we are now reading these registers using I2C Random Read which seems to work fine.