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TLV320AIC3104: Chip application problem

Tonyx.wu
Genius 3995 points
Part Number: TLV320AIC3104

Tool/software:

We now encounter a customer service landline, the downlink speaker listens to a relatively low nasal tone (sample rate 8k), the ordinary phone does not have this situation (sample rate is 16k), the platform will go through the codec before the audio data exported to sound crisp.

Refer to other projects also used codec 3104, using I2S, using mclk, there is no such problem as above.

Now the difference between the two projects is that the project with nasal sound does not connect to mclk, and uses bclk. For reference, another project also uses bclk but uses DSP mode, and the sound is also crisp.

So I would like to consult:

1. What configuration needs to be changed with bclk codec driver or what exclusions are there?

2. Use bclk or do you have to use DSP mode to have no problems?

Please help to see what is the current problem and how to solve it?

Crisp sound.m4a

Deep nasal voice.m4a

  • 0
    TI__Mastermind 46625 points

    Hi,

    I need to understand the issue better to give better comments. I don't fully understand the system from the description. Could you provide a drawing or block diagram, and include sample rate and clock frequency?

    Thank you,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Genius 3995 points

    CODEC connection relationship and waveform diagram.pdf

    1.May I ask if the register configuration for some clocks needs to be changed when MCLK is replaced with BCLK?  Because in previous projects, when MCLK was replaced with BCLK, the codec manufacturer provided some register clocks that needed to be reconfigured.  So I would like to ask what parts of the codec driver need to be modified when MCLK is not connected and BCLK is connected instead, and could you provide the parameters for these modifications?

    Can you confirm this? Do not connect mclk, connect bclk, codec driver needs to change those content configuration.

    Now our driver just replaced mclk with bclk, according to previous experience, some registers should also need to be re-configured (previously provided by ti), so consult this part.

    tlv320aic3x.txt

  • 0 in reply to Tonyx.wu
    Genius 3995 points

    The question is urgent, please reply in detail as soon as possible, thank you!

  • 0 in reply to Tonyx.wu
    TI__Mastermind 46625 points

    Hi,

    If MCLK is being replaced with BCLK of the same value, the only one register needs to change, Register 102

    If BCLK is a different value, then the clock tree will need to be reprogrammed. You might have change by some integer multiple which is unintentionally creating a filter. We have a spreadsheet that can help you determine the correct PLL values here: 

    https://www.ti.com/tool/download/SLAR163

    Best regards,
    Jeff McPherson