TLV320AIC3101: Requesting Configuration for MCLK

Akshinthala Aparna

Part Number: TLV320AIC3101

Tool/software:

Hi Team,

We are using TLV320AIC3101 audio codec, MI2S line is already up. We need to generate clock for this now.
Do we need to configure the MCLK ? or Is there any CLK is available internally in absence of MCLK?

1 month ago

0 Jeff McPherson 1 month ago

TI__Mastermind 42125 points

Hi Akshinthala,

The device requires an external clock source but MCLK is not necessary. BCLK can be used as the internal clock source instead. See the clock tree below:

Section 11.3.3 contains all the details on the requirements of these clocks and their relationships.

This tool will help you determine the necessary PLL and/or Divider values: https://www.ti.com/tool/download/SLAR163/01.00.00.00

Best regards,
Jeff McPherson

0 Akshinthala Aparna 1 month ago in reply to Jeff McPherson

Prodigy 10 points

Hi Jeff,

Thanks for the reply.

Can you please guide us on how to configure the BCLK from SOC.

0 Jeff McPherson 1 month ago in reply to Akshinthala Aparna

TI__Mastermind 42125 points

Hi Akshinthala,

BCLK should be a 50% duty cycle square wave, whole amplitude is equal to IOVDD and whose frequency is determined by the following:

Sample Frequency * # of channels * bit depth or word length. For example

BCLK = 48000 * 2 * 32 = 3.072 MHz.

Best regards,
Jeff McPherson

0 Akshinthala Aparna 1 month ago in reply to Jeff McPherson

Prodigy 10 points

Hi Jeff,

We are using Qualcomm's QCM6490 chipset and TLV320AIC3101 codec. For this can you please suggest which BCLK clock configuration should be used i) PLL Disabled or ii) PLL enabled.

0 Jeff McPherson 1 month ago in reply to Akshinthala Aparna

TI__Mastermind 42125 points

Hi Akshinthala,

The CODEC_CLK must be 256*fsref. If your BCLK is a integer multiple greater than 256*fsref, then PLL is not required. If BCLK is smaller than 256*fsref then PLL is required.

Best regards,
Jeff McPherson

Audio

Audio forum

TLV320AIC3101: Requesting Configuration for MCLK