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TLV320ADC3120: ADC sampling synchronisation

aurelienr
Intellectual 370 points
Part Number: TLV320ADC3120


Tool/software:

Hello,
I did not find detailled about internal ADC operation, timings, etc.
Obviously, the ADC performs oversampling (powered by a ~6MHz clock for 48kHz range acquisition frequency) to feed the filters.
But, at what exact moment is read the ADC filtered value before transferring it to the numeric bus ? I will use TDM mode, 32kHz acquisition frequency, TDM slot size 32 bits, 2 slots enabled.

I have a specific application (radar with FSK modulation performed at 32kHz), and I need to know at what time I need to make the FSK step in function of the TDM synchronisation timing (FSYNC). Consider that the input signal keeps its frequency but change in phase, with a phase change rate of 32kHz, so I need to have a good synchronisation.
Does the ADC filtered values are sampled and help at the same time and independently of the slot number, and each value is transmitted on the corresponding slot ? Ot is the ADC filtered value sampled just before transmitting each slot ?

Thank you
Aurelien

  • 0
    TI__Expert 7940 points

    Hi Aurelian,

    Apologies for the delay.

    The Audio ADC consists of a delta sigma modulator, and a configurable decimation filter.

    The group delay and the magnitude response for different decimation filters at different sampling rates is mentioned in the datasheet:

    Thanks and Regards,

    Lakshmi Narasimhan

  • 0 in reply to Lakshmi Narasimhan Badrinarayanan
    Intellectual 370 points

    Hello,
    In my case, to simplify understanding, consider that my radar provides a signal source with a constant frequency, but wih a phase change every time I perform a FSK step, so at 32kHz approx (or 41-44, not already choosen final value). My target with a 32kHz sampling frequency is to fill a buffer with samples at the same rate of FSK modulation. So I will fill two buffers, each buffer get one value and the other one get the next value (so each buffer is filled at a 16kHz frequency), and so on. After that I will perform some FFT and other things to extract speed measurement. That works very well with this ADC in CW mode (no FSK modulation). But with this new request, the sampling timing is important to be sure that the phase I will read from each FFT buffer will be coherent.

    I'm sorry I'm not familiar at all with decimation filtering, and all the consequences on delay or phase. I suppose that the data provided in the datasheet may answer to my question but I'm not enough skilled in this domain.

    In my case, I may only consider the linear phase or the low latency operations, because the phase deviation must be very low.
    The "latency" is not really a problem for me, always very low regarding the acquisition window time.

    But what is the effect of the filter on my signal whose phase is changing at Fs frequency ? At what moment must I perform the FSK step ?

    Aurelien

  • 0 in reply to aurelienr
    TI__Expert 7940 points

    Hi Aurelien,

    Apologies, I didn't get the query completely clear, but my understanding is that the phase of the input signal will be changed at a rate of 32kHz, the same as the input sampling rate. Is that correct?

    The intent behind mentioning the group delay in the datasheet is that, any change at time t0 on the analog input will be observed at the output around 16.9 samples later (for a 32kHz sampling rate if you are using a linear-phase decimation filter.

    This was why I was pointing out to the group delay mentioned for the decimation filter of the ADC.

    Thanks and Regards,

    Lakshmi Narasimhan