PCM9211: PCM9211: The iis input of MPUIO-C cannot be given to the spdif of MPO1

Part Number: PCM9211


Hi expert,
We meet an MPO1 output issue as below.
The path AUXIN1 ->DIT -> MPO1 is verified successfully, but the path I2S input(ADC) -> SPDIF output failed

MPIO_C (I²S Input, AUXIN1)
     ↓
DIT (PCM9211 SPDIF Transmitter)
     ↓
MPO1 (SPDIF Output)
Customer want to configure 9211 according to this process, but I2S->MPO1 has been unable to measure the spdif signal(no output)


The current register configuration is as follows:

PCM9211 Read 34h = c4.
PCM9211 Read 23h = 03.
PCM9211 Read 20h = 00.
PCM9211 Read 26h = 89.
PCM9211 Read 31h = 0a.
PCM9211 Read 28h = 07.
PCM9211 Read 61h = 10.
PCM9211 Read 63h = 00.
PCM9211 Read 30h = 14.
PCM9211 Read 25h = 3f.
PCM9211 Read 2Ah = 00.
PCM9211 Read 2Bh = 00.
PCM9211 Read 6Eh = 0f.
PCM9211 Read 6Fh = 40.
PCM9211 Read 70h = 00.
PCM9211 Read 6Bh = 44.
PCM9211 Read 60h = 44.
PCM9211 Read 78h = dd.
PCM9211 Read 37h = 02.

1.With only one input source (MPIO-C), this configuration also includes IIS output (main output). The measurement of main output is normal, so it can confirm that the input is not a problem.

2.Using a fiber opt source and AUXIN4 as input, changing the 0x60h register to 0x11 can achieve spdif output from auxin4 to mpo1. The spdif signal is tested to be normal.So this configuration, MPO1 as spdif output, is also configured correctly.

But even when the 0x60h register is 0x44, MPO1 pin cannot detect the spdif signal.
Input clock = 24.576MHz active crystal oscillator (only connected to XT1)

Please help suggest the possible issue and register configuration/check points
Screenshot 2025-10-17 200114.jpg

System block
 
de4ac035b1b02386aeabc0b619053989.jpeg

  • Hi , To make it easier to see the possible issue, can you identify the path that you are choosing in the block diagram with specific registers? 

    It makes more sense if I know which path is  intended to select with the selected registers above.

    Meanwhile I am attaching the main script that I have , may be they can start from the attached script and do modifications to route it as they desire.


    #**************************************
    #this script is for SPDIF-->RXIN0-->DIR-->MainOutput, Record sound from SPDIF to PC through TAS1020
    
    #So
    #1, Chose RXIN0 to DIR
    #2, Active DIR
    #3, chose DIR output as Mainoutput's source.
    
    #Also HW modification
    #1, Flying to High Level(3.3V) to make sure U7's output is Hi-Z
    #or 2, TAS1020 output logic high on P1.2 I2S enable signal. 
    #**************************************
    
    
    #System RST Control
    #w 80 40 00
    w 80 40 33
    w 80 40 C0
    
    #XTI Source, Clock (SCK/BCK/LRCK) Frequency Setting
    # XTI CLK source 12.288 and BCK 3.072, LRCK 48k = XTI/512
    w 80 31 1A
    w 80 33 22
    w 80 20 00
    w 80 24 00
    #ADC clock source is chosen by REG42
    w 80 26 81
    
    #XTI Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting
    w 80 33 22
    
    
    #*********************************************************
    #-------------------------------Start DIR settings---------------------------------------
    #REG. 21h, DIR Receivable Incoming Biphase's Sampling Frequency Range Setting
    w 80 21 00
    
    #REG. 22h, DIR CLKSTP and VOUT delay
    w 80 22 01
    
    #REG. 23h, DIR OCS start up wait time and Process for Parity Error Detection and ERROR Release Wait Time Setting
    w 80 23 04
    
    # REG 27h DIR Acceptable fs Range Setting & Mask
    w 80 27 00
    
    # REG 2Fh, DIR Output Data Format, 24bit I2S mode
    w 80 2F 04
    
    # REG. 30h, DIR Recovered System Clock (SCK) Ratio Setting
    w 80 30 02
    
    #REG. 32h, DIR Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting
    w 80 32 22
    
    #REG 34h DIR Input Biphase Signal Source Select and RXIN01 Coaxial Amplifier
    #--PWR down amplifier, Select RXIN2
    #w 80 34 C2
    #--PWR up amplifier, select RXIN0
    w 80 34 00
    #--PWR up amplifier, select RXIN1
    #w 80 34 01
    
    #REG. 37h, Port Sampling Frequency Calculator Measurement Target Setting, Cal and DIR Fs
    w 80 37 00
    #REG 38h rd DIR Fs
    r 80 38 01
    #***********************************************************
    #------------------------------------ End DIR settings------------------------------------------
    
    
    #***********************************************************
    #---------------------------------Start  MainOutput Settings--------------------------------------
    #MainOutput
    #REG. 6Ah, Main Output & AUXOUT Port Control
    w 80 6A 00
    
    #REG. 6Bh, Main Output Port (SCKO/BCK/LRCK/DOUT) Source Setting
    w 80 6B 11
    
    #REG. 6Dh, MPIO_B & Main Output Port Hi-Z Control
    w 80 6D 00
    #***********************************************************
    #------------------------------------ End MainOutput settings------------------------------------------
    
    # read back all registers to ensure GUI integrity
    r 80 20 5E

    Regards,

    Arash

  • Hi  Arash

    Thanks for guide, after checked more on hardware side, the issue is caused by MPIO_C MCLK connection. The ticket can be closed now.

    -Thomas

  • Thanks for letting me know. I will close the ticket.

    Regards,

    Arash