Part Number: TLV320ADC6140
Hello E2E Experts,
Good day.
I control TLV320ADC6140 over a SPI (2 MHz clock). From time to time are loaded different configurations, that involve updating following registers of the IC. Lets name:
Configuration A (PGA gain 8dB):
SpiWrite2(0xd6, 0x00); //AudioSetDecimatorFilter
SpiWrite2(0x28, 0xdd); //AudioSetSampleRate
SpiWrite2(0x7c, 0xc9); //AudioSetDvol
SpiWrite2(0x90, 0xc9); //AudioSetDvol
SpiWrite2(0x7a, 0x20); //AudioSetGain
SpiWrite2(0x8e, 0x20); //AudioSetGain
SpiWrite2(0x7e, 0x80); //AudioSetCal
SpiWrite2(0x92, 0x80); //AudioSetCal
SpiWrite2(0x80, 0x00); //AudioSetPhase
SpiWrite2(0x94, 0x00); //AudioSetPhase
Configuration B (PGA gain 9dB):
SpiWrite2(0xd6, 0x00); //AudioSetDecimatorFilter
SpiWrite2(0x28, 0xdd); //AudioSetSampleRate
SpiWrite2(0x7c, 0xc9); //AudioSetDvol
SpiWrite2(0x90, 0xc9); //AudioSetDvol
SpiWrite2(0x7a, 0x24); //AudioSetGain
SpiWrite2(0x8e, 0x24); //AudioSetGain
SpiWrite2(0x7e, 0x80); //AudioSetCal
SpiWrite2(0x92, 0x80); //AudioSetCal
SpiWrite2(0x80, 0x00); //AudioSetPhase
SpiWrite2(0x94, 0x00); //AudioSetPhase
The difference between is only in the PGA values.
The transfers are sent in the listed order, no other registers are modified, the ADC is fully operational and not stopped, DRE and AGC disabled.
What I notice is when the current configuration is A and send update to B, in many cases the first channel level is around 0.5dB lower. The problem is traced to the channel gain calibration register (0x39 = 0x72>>1). If later is updated only that register, the issue disappears.
With less chance, the other channel sometimes is 0.5dB lower or both are with correct level.
Never had a problem when update from B->A, or A->A or B->B.
The SPI signals are recorded with a oscilloscope, and checked that match the desired data.
Regards,
TICSC
