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TAD5212EVM-K: TAD5212 DAC out plus PDM MIC via I2S - not working

Part Number: TAD5212EVM-K
Other Parts Discussed in Thread: TAD5212, , TAD5212-Q1

Trying to evaluate TAD5212 with TAD5212EVM-K I do NOT get DAC out (via USB from PC) PLUS PDM MICs (via USB to PC) working.

I can configure for clear DAC out OR PDM in. But the configuration differs, mainly on setting the
I2S format (register 0x1A):
For DAC out I need 1A=70 - works fine.
For PDM MIC in I need 1A=60 - works fine.

But combining both, DAC out and PDM MIC in - FAILS:
- with reg. 1A=60 - the DAC out channel 2 (right) is "wrong" (noise, distorted, quieter) = PDM in is ok
- with reg. 1A=70 - DAC out is correct, but now PDM in is full of noise, distortion (it works a bit to hear)

Strange is also the behavior on registers 0x20, 0x21 (PDM slots) and 0x52, 0x57 (PDM MIC volume):
- it works fine if 24bit configured (reg. 1A=60)
- but with 32bit (reg. 1A=70) the register 1F must be different (reg 1F=30 vs. 1F=21),
  based on datasheet and comparing with DAC slot settings, actually 1F=21 makes sense, not 30)
- and the volume setting for PDM channel 1, 2 behaves strange (reg. 57 controls both channels, reg. 52 does
   not matter what I set, I can mute reg. 52 - still a signal, I can set via reg. 57 the volume for both channels)

So, combining DAC out PLUS PDM in - fails.

At the end my I2C config file.
Here two waveform captures for I2S signals.
Strange is:
- configured as I2S but it looks still like TDM (FS is just a pulse, not stable during entire left channel, but OK, it seems to work)
   BTW: this I2S signal waveform is generated by the XMOS AC-MB (nothing to blame on TAD5212,
   running as a slave)
- even it seems to be handled properly by the XMOS AC-MB - it is still a 8 slot I2S signal
   (see BCLK as 12.288 MHz, FS as 48 KHz, as 8x32bit slots still)

TAD5212.png

Figure 1: I2S waveform (generated by XMOS AC-MB): 8 slot I2S with FS as a pulse (like TDM, but working as I2S setting and only if I2S is selected, XMOS does not seem to handle it as TDM)

TAD5212_2.png

Figure 2: PDM in signal (channel 2, red): it is a 32bit I2S data frame!

My assumption:

The I2S timing generated is wrong (for PDM in, DOUT to USB). Or DOUT jitters a lot, does not come at the right time, is sometimes shifted by one clock edge (interleaving right and left channel values).

The USB drivers on PC uses 24bit, 48KHz (set as 2 channels for USB/DAC out, 8 channels for USB/PDM in).
The I2S to DAC is correctly a 32bit frame with 24 valid bits (OK, the LSBs are zero in 32bit data frame).
But the PDM in is also a 32bit - but now with all 32bits valid and used!
If this DOUT signal comes just a bit too late, with jitter, the LSB can go as MSB for the other channel.
This is what seems to happen (the PDM channel DOUT is not correct for the USB stream to PC).
This creates heavy noise, distortions.

If PDM MIC is set to 24bit - it is clear: obvious: now the lowests bits are also zero and even they would slip into next channel as MSBs - still OK (not setting MSB for other channel).

Configuring 24bit for DAC out (which fails) might be reasonable, e.g. now the frame is just 24bit but
the XMOS I2S to USB wants to see 32bit slots. (actually not clear how to set 24bits valid data for a 32bit frame)

So, it fails mainly by:
- configure 32bit slots (reg. 1A = 70)
- and get the PDM MIC DOUT signal out (via USB to PC) properly
  (PDM MIC wants to use 24bit!)

Here my I2C configuration and watch for the comments on registers 0x1A, 0x1E, 0x1F (and 0x52, 0x57).
The volume setting for PDM channels (reg. 0x52, 0x57) behaves strange when on 32bit mode (reg. 1A=70).

w a0 00 00  #page 0
w a0 01 01
w a0 00 00  #page 0
w a0 02 09
w a0 0a 41  #PDMCLK = GPIO1
w a0 0d 02  #GPI1 = input or other function
w a0 10 51  #DOUT ss ASI DOUT
w a0 13 cc  #PDM DATA config
#w a0 19 00  #default
w a0 1a 70	#0x60 for MIC USB in, 0x70 for USB out !!!!!
w a0 1e 20  #PDM MIC slot - STRANGE!
w a0 1f 21  #PDM MIC slot - STRANGE! - why 0x30? not 0x21, 0x30 works on 1a=60??
#if reg 1a-70 -> set 1f=21 !!!!!
w a0 20 00
w a0 21 00
w a0 28 20  #DAC out slot - default
w a0 29 21  #DAC out slot - default - noise with reg. 1a = 60 !!!!!
#left channel ok, right channel works only with reg 1a = 70
w a0 35 00
w a0 52 f0  #PDM MIC volume - default A1 - STRANGE - does not matter as long reg 0x57
w a0 57 f0  #PDM MIC volume - default A1 - STRANGE - mutes both! different volume!
#creates heavy noise and just 57=01... is same volume (if reg 1a=70)!
w a0 64 30
w a0 65 61
w a0 6b 30
w a0 6c 61
w a0 73 08
w a0 76 cc
w a0 00 03
w a0 38 09
w a0 39 28
w a0 3a 26
w a0 3b 20
w a0 3c 00
w a0 3d 00
w a0 3e 09
w a0 48 01
w a0 49 01
w a0 00 0a
w a0 79 fd
w a0 7a db
w a0 7b 01
w a0 7c 80
w a0 7d 02
w a0 7e 24
w a0 7f ff
w a0 00 0b
w a0 08 7f
w a0 09 fb
w a0 0a b6
w a0 0b 01
w a0 00 11
w a0 4a 00
w a0 00 19
w a0 6f 0f
w a0 00 1a
w a0 1e 00
w a0 3a 00
w a0 40 00
w a0 41 0a
w a0 42 5c
w a0 43 b6
w a0 44 e0
w a0 45 00
w a0 46 00
w a0 47 00
w a0 00 1b
w a0 66 00
w a0 67 08
w a0 6a 00
w a0 6e 80
w a0 7a 00
w a0 7b 05
w a0 00 1c
w a0 24 0c
w a0 25 cc
w a0 26 cc
w a0 27 cc
w a0 28 7f
w a0 29 ff
w a0 2a ff
w a0 2b ff
w a0 34 08
w a0 43 01
w a0 52 03
w a0 53 c0
w a0 00 00
w a0 78 C0 #enable PDM and DAC channels
  • Hi Torsten,

    I think there may be a clock synchronization error here. Firstly, this device only supports up to 4 channels of PDM mics. Secondly, I2S can only support 2 channels. To configure properly with I2S, you would need to output 2 PDM channels on DOUT and 2 PDM channels on the second data line DOUT2. You would have to configure a GPIO (maybe GPIO2) as DOUT2.

    So in this case, you would have 2 channels of DAC data on DIN (CH1 on left slot 0 and CH2 on right slot 0), 2 channels of PDM on DOUT (CH1 on left slot 0 and CH2 on right slot 0), and 2 channels of PDM on DOUT2 (CH3 on left slot 0 and CH4 on right slot 0), with a BCLK of 2*32*48kHz = 3.072MHz, and they all will be synchronized with 0x1A = 0x70.

    Let me know what you think about this.

    Best,

    Garret

  • "Hmmmm".
    The I2S signal generated (as illustrated) is still an 8 slot (x 32bit) signal. I use only the two PDM MICs on eval board (two slots and two ADC/PDM channels).
    As I understand (see also the setting for the USB to Eval DIN, coming out on DAC): it has to be set as: left slot 0 and left slot 1.
    Makes sense for an I2S frame (when FS signal covers 8 slots!): so, now left and right I2S data words come as on "regular I2S", after each other,
    as lost 0 and slot 1 after FS triggered.

    I assume I "should" to set also for MIC to USB host (as I2S DOUT, Tx channels in TAD5212) in a similar way (reg. 1E=20, 1F=21), left slot 0 and left slot 1,
    so that the first two slots are used (as on I2S).

    I did a test:

    • disable DOUT (reg. 10=00) ! BTW: reg. 10=50 as "Hi-Z output" does NOT work! (it is driven!!!!)
    • so, the DOUT1 signal on AC-MB is floating (not driven by TAD5212)
    • connect on AC-MB DOUT1 with DIN1 (feedback DIN to DOUT)

    And: IT WORKS!!!

    I feed back the same I2S data signal (playing from host PC) as the input signal (MIC to host PC in).
    This is clear sound and it comes back properly to host PC.

    Confirming my assumption:

    • it is an issue with the DOUT timing!
    • the TAD5212 sends the signal towards the host PC a bit "too late": the bits interleave a 32bit channel packet
    • or: the MSB of DOUT jitters

    Bear in mind:
    The AC-MB board (with the XMOS chip) is designed also for TDM, with 8 slots (always).
    Configuring TAD5212 for "I2S" looks still like a TDM signal: it is "I2S with 8 slots". You can also clearly see it with the BCLK as 12.288 MHz (with 48 KHz FS),
    Otherwise, as "correct" I2S signal it should be 3.072 MHz and the FS signal is high during 32bits, during the 32bit for left channel PCM data word.
    But it is not this way (due to XMOS FW on AC-MB).
    FS is still a one clock cycle pulse (even in I2S mode, but might be OK for XMOS).

    Detailed analysis and my conclusion:

    It looks like something is wrong on the DOUT timing (for the ADC/PDM to I2S for USB):

    • the setup and hold timing for the DIN (from USB PC to DAC) looks perfect - OK
    • but the setup and hold timing for the DOUT (to PC) looks strange, esp. on the MSB bit!
    • if the MSB on DOUT "jitters" - no wonder why I get so much noise (and still part of the signal sounds correct underneath the noise)
      (a randomly "jumping" MSB creates a half-swing amplitude noise - what I hear)

    Figure 1: DOUT and DIN on AC-MB as same signal - OK

    Figure 2: DOUT (on MC-AB) as ADC/PDM via USB to host

    Figure 3: DOUT looks a bit shifted and "too late"?

    Figure 4: actually, the MSB of DOUT seems to "jitter" (very short hold time here)

    Figure 5: the MSB of DOUT seems to be always "at the corner"

    Figure 6: the hold time of DOUT is just 8 ns - maybe sometimes it come before the raising edge of BLCK?

    DOUT looks completely different in terms of setup and hold-time in relation to the DIN signal.
    If DOUT "jitters" and the MSB is sampled wrong - heavy distortion (and noise)

    Please, could you try to setup and configure TAD5212 for DIN and DOUT in parallel?
    What do you see?

    I do not think the DOUT is shifted by one bit: towards the end of the data word it looks better (larger setup and hold), mainly the MSB looks suspicious.
    It seems to be mainly a problem about "when the MSB is sent".

    I do not assume that my register config is still wrong (what would cause a shift of DOUT data words?).

  • BTW:
    if I configure other slots for DOUT, e.g. "left slot 2" - I see that the data word is now shifted (into slot 2).
    Change reg. 1F=22

    So, it confirms clearly: the I2S signal is still an 8-slot (a 32bit) signal.

    Figure 1: DOUT reg. 1F=22 - now right channel is in left slot 2!

    When I configure reg. 1F=30 - as mentioned the TAx5x12EVM-K manual, page 32, "##### Record from DMIC Test ######",
    i results in just all noise (and still stereo, no idea why, because waveform shows there is not a right channel active)!
    it uses also reg. 1A=70 (32bit, obvious) - but this example seems to be wrong.

    Figure 2: DOUT reg. 1F=30 - according to manual - just all noise (stereo!, even no right channel in I2S to see).

    What is this?
    What is the correct config to get ADC/PDM out via USB and AC-MB?

  • Hi Torsten,

    Thank you for the detailed description. I will work on testing this on an EVM next week and respond here with my results.

    Best,

    Garret

  • It works now!
    But unfortunately it confirms: there is a bug in TAD5212 chip

    The bug is:

    • when you configure PASI as I2S, 32bit (needed for XMOS USB) - this setting is "global"
      (it sets for DOUT and DIN on PASI)
    • but the DOUT (the PDM MIC channels as I2S to XMOS, USB to host PC)
      IS DELAYED by one (or almost one) BCLK cycle!

    How to get it working?:

    • configure TDM (affecting DIN and DOUT, now DIN (USB from host PC) is wrong, reg. 1A=30)
    • but add for DIN (DAC out, USB from host PC) one additional BCLK delay (reg. 26=01)

    Please, find my working I2C config script at the end.
    Technically, TAD5212 runs now in TDM mode. In order to make it I2S compliant (for XMOS I2S) - the data (DIN) must be shifted by one clock cycle.
    DOUT (PDM MIC to USB host) is already shifted, nothing to add in config ("the bug" taken into account).

    Waveforms confirming DOUT timing is wrong (in I2S mode):

    Figure 1: the DOUT signal (PDM MIC via USB to PC) is shifted by one BCLK cycle (in I2S mode adding additional shift of DOUT, becoming "too late")

    Figure 2: with TDM config DOUT and DIN are working (needing the tweak to shift DIN to make it I2S compliant for XMOS I2S )

    Working I2C config script:

    #working config for DAC out and PDM MIC in
    w a0 00 00  #page 0
    w a0 01 01
    w a0 00 00  #page 0
    w a0 02 09
    w a0 0a 41  #PDMCLK = GPIO1
    w a0 0d 02  #GPI1 = input or other function
    w a0 10 51  #DOUT as ASI DOUT  =51 (=00 is DOUT floating)
    w a0 13 cc  #PDM DATA config
    #!!!!! it must be TDM and clk offset tweaked - I2S FAILS !!!!!
    w a0 1a 30	#0x30 for MIC USB in, 0x70 for USB out !!!!!
    #optional (works in the same way!
    #w a0 1c 1f  #TDM reg. 1a=30 and offset - works also for PDM MIC
    w a0 26 01  #DAC out TDM with one clk shifted!
    w a0 1e 20  #PDM MIC slot
    w a0 1f 21  #PDM MIC slot - STRANGE! - why 0x30? not 0x21 - must be 21
    w a0 20 00
    w a0 21 00
    w a0 28 20  #DAC out slot - default
    w a0 29 21  #DAC out slot - default - DIN and DOUT with identical slot config!
    w a0 35 00
    w a0 52 f4  #PDM MIC volume - default A1
    w a0 57 f4  #PDM MIC volume - default A1
    w a0 64 30
    w a0 65 61
    w a0 6b 30
    w a0 6c 61
    w a0 73 08
    w a0 76 cc  #PDM and DAC channels
    w a0 00 03
    w a0 38 09
    w a0 39 28
    w a0 3a 26
    w a0 3b 20
    w a0 3c 00
    w a0 3d 00
    w a0 3e 09
    w a0 48 01
    w a0 49 01
    w a0 00 0a
    w a0 79 fd
    w a0 7a db
    w a0 7b 01
    w a0 7c 80
    w a0 7d 02
    w a0 7e 24
    w a0 7f ff
    w a0 00 0b
    w a0 08 7f
    w a0 09 fb
    w a0 0a b6
    w a0 0b 01
    w a0 00 11
    w a0 4a 00
    w a0 00 19
    w a0 6f 0f
    w a0 00 1a
    w a0 1e 00
    w a0 3a 00
    w a0 40 00
    w a0 41 0a
    w a0 42 5c
    w a0 43 b6
    w a0 44 e0
    w a0 45 00
    w a0 46 00
    w a0 47 00
    w a0 00 1b
    w a0 66 00
    w a0 67 08
    w a0 6a 00
    w a0 6e 80
    w a0 7a 00
    w a0 7b 05
    w a0 00 1c
    w a0 24 0c
    w a0 25 cc
    w a0 26 cc
    w a0 27 cc
    w a0 28 7f
    w a0 29 ff
    w a0 2a ff
    w a0 2b ff
    w a0 34 08
    w a0 43 01
    w a0 52 03
    w a0 53 c0
    w a0 00 00
    w a0 78 c0  #enable PDM and DAC channels

    See these registers:

    w a0 1a 30 #0x30 for MIC USB in, 0x70 for USB out !!!!! it sets TDM mode (not I2S)!

    w a0 26 01  #DAC out TDM with one clk shifted!

    w a0 1e 20 #PDM MIC slot
    w a0 1f  21 #PDM MIC slot - STRANGE! - why 0x30? not 0x21 - must be 21

    BTW: the ##### Record from DMIC Test ##### in TAx5x12EVM-K manual, page 32 - is wrong

  • BTW: you could "invert the bug" as:
    "if you configure TDM - and you want to sample/use as TDM - the DOUT (PDM to I2S) will not work"
    (this data line should now delayed by one clock cycle and TDM never working).

    My EVAL board has a chip soldered, marked as:

    • TAX5LV4
    • TI 468
    • AGQ7

    The chips ordered show:

    • TAD5212
    • TI 488
    • APXF

    Is my EVAL board assembled with an early spin version (e.g. A0) but the chips to order are a newer spin (e.g. B0), with a bug fix?
    I could not find any Errata document (is TAD5212 "bug free"?).

    JOKING:
    If you (company TI) would confirm as: "yes, I2S config has an issue with DOUT",
    please, could you send me an EVAL board with the latest version of a TAD5212-Q1 soldered on it?
    Thank you.

  • Hi Torsten,

    Apologies for not catching this earlier, but I see the issue clearly now - and it is due to the XMOS, not our device the TAD5212. The XMOS cannot recognize the true I2S protocol with left and right channels - it can only interface with TDM as you noticed.

    Because of this, to send audio via USB, you will have to configure the TAD5212 in TDM mode. Also, the XMOS introduces a one bit delay on its DOUT, which is why the RX OFFSET must be set (register 0x26 = 0x01) as you found.

    So this is not a bug in the chip, but rather accommodating for the limitations of the XMOS.

    In order to use configure the device with I2S mode, you must supply the clocks via the External ASI pins on the bottom edge of the AC-MB.

    Best,

    Garret

  • Thank you.
    Makes sense. Will there be a FW update for the XMOS AC-MB?

  • Hi Torsten,

    Not that I am aware of, as the XMOS is not a TI device.

    Best,

    Garret