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TAC5212: CM5 Bring Up

Shemaiah Rangitaawa
Prodigy 40 points

Part Number: TAC5212

Hello, I've been having some trouble porting the TAC5x1x drivers to the Raspberry Pi Compute Module 5. I've managed to get the drivers installed and the soundcard is visible in ALSA, however no audio output has been achieved. Sometimes a small blip occurs when audio is played but other than that it's silent.

We're using the linux drivers written here: https://git.ti.com/cgit/lpaa-android-drivers/tac5x1x-linux-driver/tree/. The I2C address of the codec is 0x50 and the codec is connected on the I2S0 bus of the CM5 with the I2S0_SCLK signal on GPIO18.

I have linked text files with the output of various commands confirming the soundcard presence in ALSA and available symbols in the device tree.

I've modified the DTS from the Pi 4b to support the CM5's RP1 BCM2712 cpu. I'm not so sure if my modifications are valid and will function as I intend, especially with reguard to the I2S clock signals so any guidance would be appreciated.

tac5x1x-cm5-overlay.txt

sound card stats.txt

__symbols__.txt 

  • 0
    TI__Genius 17300 points

    Hi,

    Are you able to measure the I2S clocks at the codec? This would be WCLK, BCLK, and potentially CCLK. 

    Also, there is a Raspberry Pi example configuration and document in the doc/ folder of the Linux driver TI git repo: https://git.ti.com/cgit/lpaa-android-drivers/tac5x1x-linux-driver/tree/doc

    https://git.ti.com/cgit/lpaa-android-drivers/tac5x1x-linux-driver/plain/doc/Raspberry%20Pi%204B%20bring%20up%20&%20Driver%20Porting.pdf

    Let me know about this and what you think of the example...

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 40 points

    It will take a while for me to be able to measure the signals to the codec, we've designed a custom prototype PCB and simply forgot to include test pads on the I2S bus. I'll scrape the soldermask and probe the traces then get back to you with that.

    Only BCLK, FSYNC, DOUT, and DIN is used, I'm unsure what the other clocks you've mentioned are. 

    The example configuration from the Pi 4b is what I've modified for compatibility with the CM5. I've changed bcm2835 to bcm2712, tac5411 to tac5212, changed a few of the hardware and routing functions otherwise it's mostly the same. 

    We're using kernel rpi-v6.12.y, the example DTS was tested with rpi-v6.7.y branch so perhaps starting from a fresh image and reverting to the old kernel version could help? 

    To clarifiy the issue, I'm only geting a single crackle or pop or blip noise when I play any audio on the CM5, the codec appears in ALSA and I can adjust various parameters in alsamixer, drivers are properly installed and are visible with: lsmod | grep tac, all depends are installed, yet no audio output is achieved.

  • 0 in reply to Shemaiah Rangitaawa
    TI__Genius 17300 points

    Hi,

    Let me know about the clocks when you are able. Do you get a pop at the beginning of any audio file you play or just on startup? If just on startup, it may just be the output drivers charging up. I am concerned about the clocks the most I think - where does " clock-frequency = <400000>;" come from? Which clock has a frequency of 400kHz? This is not a standard audio frequency which is why I ask. Can you share a register dump of the codec here as well?

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 40 points

    Will do. I get a pop/crackling noise whenever an audio files plays or stops, it will reliably produce a low amplitude crackle noise when I play any audio file, even lower amplitude when audio is stopped. "clock-frequency = <400000>" comes from the example DTS shared in the git repo, I think it's i2c clock rate not audio clock rate.

    I have attached the clock config registers in BOOK0_P0 and a dump of main device configuration registers, page 0, 1, and 3 of the codec.

    Fullscreen tac5212_reg_dump.txt Download 
    BOOK0_P0 0x32  CLK_CFG0         Clock configuration register 0                          reset=0x00  value=0x50
BOOK0_P0 0x33  CLK_CFG1         Clock configuration register 1                          reset=0x00  value=0x00
BOOK0_P0 0x34  CLK_CFG2         Clock configuration register 2                          reset=0x40  value=0x40
BOOK0_P0 0x35  CNT_CLK_CFG0     Controller mode clock configuration register 0          reset=0x00  value=0x00
BOOK0_P0 0x36  CNT_CLK_CFG1     Controller mode clock configuration register 1          reset=0x00  value=0x00
BOOK0_P0 0x37  CNT_CLK_CFG2     Controller mode clock configuration register 2          reset=0x20  value=0x20
BOOK0_P0 0x38  CNT_CLK_CFG3     Controller mode clock configuration register 3          reset=0x00  value=0x00
BOOK0_P0 0x39  CNT_CLK_CFG4     Controller mode clock configuration register 4          reset=0x00  value=0x00
BOOK0_P0 0x3A  CNT_CLK_CFG5     Controller mode clock configuration register 5          reset=0x00  value=0x00
BOOK0_P0 0x3B  CNT_CLK_CFG6     Controller mode clock configuration register 6          reset=0x00  value=0x00
BOOK0_P0 0x3C  CLK_ERR_STS0     Clock error and status register 0                       reset=0x00  value=0x00
BOOK0_P0 0x3D  CLK_ERR_STS1     Clock error and status register 1                       reset=0x00  value=0x00
BOOK0_P0 0x3E  CLK_DET_STS0     Clock ratio detection register 0                        reset=0x00  value=0x50
BOOK0_P0 0x3F  CLK_DET_STS1     Clock ratio detection register 1                        reset=0x00  value=0x00
BOOK0_P0 0x40  CLK_DET_STS2     Clock ratio detection register 2                        reset=0x00  value=0x00
BOOK0_P0 0x41  CLK_DET_STS3     Clock ratio detection register 3                        reset=0x00  value=0x00

===== PAGE 0x00 =====
0x00: 0x00 0x00 0x01 0x00 0x00 0x15 0x35 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00
0x10: 0x52 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x70 0x00 0x00 0x00 0x20 0x21
0x20: 0x02 0x03 0x04 0x05 0x06 0x07 0x00 0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
0x30: 0x00 0x00 0x50 0x00 0x40 0x00 0x00 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x00
0x40: 0x00 0x00 0x10 0x54 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x2e 0x00 0x00 0x00
0x50: 0x04 0x00 0xa1 0x80 0x00 0x04 0x00 0xa1 0x80 0x00 0x00 0xa1 0x80 0x00 0x00 0xa1
0x60: 0x80 0x00 0x00 0x00 0x20 0x20 0x20 0xc9 0x80 0xc9 0x80 0x20 0x20 0x20 0xc9 0x80
0x70: 0xc9 0x80 0x18 0x18 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x00 0xc0 0x10 0xb2 0x00

===== PAGE 0x01 =====
0x00: 0x01 0x00 0x00 0x00 0x00 0x01 0x10 0x00 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x10: 0x00 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x20 0x80
0x20: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x00 0x00 0xbf 0xff
0x30: 0x0f 0x00 0x00 0x30 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x00 0x00 0x00
0x40: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x37 0x87 0x00 0xb8 0x00 0xa2 0x48 0xba 0x4b
0x50: 0x88 0x40 0x44 0x00 0x48 0x00 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x00 0x04
0x60: 0x00 0x05 0x00 0x06 0x00 0x07 0x00 0x08 0x00 0x09 0x00 0x0a 0x00 0x0b 0x00 0x0c
0x70: 0x00 0x0d 0x00 0xa0 0x00 0x70 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

===== PAGE 0x03 =====
0x00: 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x10: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x00 0x00 0x00 0x00 0x01
0x20: 0x02 0x03 0x04 0x05 0x06 0x07 0x00 0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
0x30: 0x00 0x00 0x00 0x00 0x10 0x01 0x00 0x00 0x08 0x20 0x04 0x00 0x01 0x01 0x01 0x00
0x40: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x50: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x60: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x70: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

  • 0 in reply to Shemaiah Rangitaawa
    TI__Genius 13795 points

    Hi Shemaiah,

    Please expect an update next week as our team is on holiday.

    Best,

    Garret

  • 0 in reply to Garret Godfrey
    Prodigy 40 points

    Apologies, while scoping the I2S bus I realized I had I2S0_SDO going to the DOUT pin of the codec and I2S0_SDI to DIN, flipped the signals around and finally got audio output!

    However, it was only out of channel 1, there was no output from channel 2. Spent a day figuring out what could possibly be disabiling OUT2 while OUT1 is functional, dug through datasheets, the kernel overlay, online forums, learned more about TDM/I2S protocols just to find answers and got nowhere. Until, I checked the git repo again and realized there were other branches, switched to the latest tac5x1x-driver branch, installed that driver on the CM5 and finally got a complete stereo differential line level output.

    Anyway, hope you guys had a great holiday and that this information helps someone in the future. The issue is resolved Slight smile.