TLV320AIC3254: Updating the clock and PLL settings runtime

Oskar Brattberg

We have two main sources for audio in our solution. Analog path where we get the audio from IN2 from two microphones and digital path from I2S. Running AGC on the analog microphones.

When running only analog we use a 4MHz clock in on MCLK and the AGC works great.

Then when we switch to I2S we run the PLL on BCLK from I2S at ~1,4MHz and the both the analog audio and I2S audio works but it seems the AGC does not run any longer.

If we reapply the PLL and clock setting a second time (still same register settings) the AGC seams to work.

What is the correct way to make sure the PLL and ADC/AGC start when updating settings runtime? I would really prefer not to restart the entire DSP due to delays etc.

3 months ago

0 Mir Jeffres 3 months ago

TI__Genius 17450 points

Hi,

How are you configuring the device? Can you share a register config script that you run when you connect the clocks and the corresponding change? If you can send a register dump during each config that would be helpful as well. I think the AGC does not have much to do with the PLL but maybe the AGC registers are overwritten when you switch your configuration.

Best,
Mir

0 Oskar Brattberg 3 months ago

Prodigy 55 points

/**
 * @file dsp_bluetooth.hpp
  * @brief This file contains the DSP settings for the 
 * Blutetooth variant
 * 
 */

#pragma once

#include "dsp_conf_common.hpp"
#include <array>
#include <cstdint>

namespace dsp_config::bluetooth {

#include "mini_dsp/bt_shooter.hpp"

constexpr std::uint16_t POWER_UP_COMMAND_COUNT{4};
constexpr std::array<std::uint8_t, POWER_UP_COMMAND_COUNT * COMMAND_SIZE>


    POWER_UP_COMMANDS{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x01, 0x08, // RA 01h/01h: disable weak AVDD and DVDD connection
        0x02, 0x51, // RA 01h/02h: DLDO - ON/1.67(V), ALDO - ON/1.67(V), ANALOG BLOKS - ON
        0x7B, 0x05  // RA 01h/7Bh: Force 40ms reference power up
        // clang-format on
    };

constexpr std::uint16_t INIT_COMMAND_COUNT{33};
constexpr std::array<std::uint8_t, INIT_COMMAND_COUNT * COMMAND_SIZE>
    INIT_COMMANDS{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x0A, 0x40, // FCCM - 0.75 V
        0x00, 0x00, // PAGE 0
        0x0B, 0x81, // NDAC divider powered up, divding coefficient 1
        0x0C, 0x82, // MDAC divider powered up, dividing coefficient 2
        0x13, 0x82, // MADC divider powered up, dividing coefficient 2
        0x14, 0x40, // ADC Oversampling rate 64
        0x0D, 0x00, // DAC Oversampling rate 64 (MSB)
        0x0E, 0x40, // DAC Oversampling rate 64 (LSB)
        0x1B, 0x0C, // BCLK and WCLK - outputs
        0x1D, 0x01, // BDIV_CLKIN = DAC_MOD_CLK
        0x1E, 0x81, // BDIV - ON, BCLK = ADC_MOD_CLK/1 - about 1MHz
        0x21, 0x10, // WCLK = ADC_FS
        0x00, 0x01, // PAGE 1
        0x47, 0x31, // Analog input power-up time set to 3.1(ms)
        0x00, 0x00, // PAGE 0
        0x41, 0xD0, // DAC Left Volume -24dB
        0x42, 0xD0, // DAC Right Volume -24dB
        0x3D, 0x08, // PRB_R8 ADC signal processing selected block PRB_R8
        0x00, 0x01, // PAGE 1
        0x14, 0xCD, // HP soft routing step 200(ms), HP power amp power in 0.725 time const 6k/47uF
        0x0C, 0x02, // HPL routing: MAL
        0x0D, 0x02, // HPR routing: MAR
        0x18, 0x28, // MAL level mute
        0x19, 0x28, // MAR level mute
        0x09, 0x03, // power up MAL and MAR
        0x10, 0x16, // HPL gain 22 dB
        0x11, 0x16, // HPR gain 22 dB
        0x09, 0x33, // power up MAL, MAR, HPL and HPR
        0x3D, 0xFF, // PTM_R1 ADC Power tune mode
        0x16, 0x40, // IN1L to HPL gain -32.1dB
        0x17, 0x40, // IN1R to HPR gain -32.1dB
        0x33, 0x58, // MICBIAS on, 1.4V
        // clang-format on
    };

constexpr std::uint16_t POWER_OFF_COMMAND_COUNT{4};
constexpr std::array<std::uint8_t, POWER_OFF_COMMAND_COUNT * COMMAND_SIZE>
    POWER_OFF_COMMANDS{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x02, 0x08, // Power down analog blocks
        0x09, 0x00, // Turn amplifiers off
        0x33, 0x10  // Power off MICBIAS and set it to 1.425(V)@CM=0.75(V);;
        // clang-format on
    };

// ADC fs = 4MHz/2/64 = 31250
// Attack time = 480 / 31250 = 0.015360 s
// Decay time = 8704 / 31250 = 0.2785 s
constexpr std::uint16_t HUNTING_COMMAND_COUNT{20};
constexpr std::array<std::uint8_t, HUNTING_COMMAND_COUNT * COMMAND_SIZE> HUNTING_COMMANDS{
    // clang-format off
        0x00, 0x01, // PAGE 1
        0x0C, 0x02, // HPL routing: MAL
        0x0D, 0x02, // HPR routing: MAR
        0x18, 0x23, // MAL level -20.6dB
        0x19, 0x23, // MAR level -20.6dB
        0x10, 0x16, // HPL is not muted, HPL gain +22dB
        0x11, 0x16, // HPR is not muted, HPR gain +22dB
        0x00, 0x00, // PAGE 0
        0x56, 0xE0, // Enable left channel AGC, set target level to -20dBFS, hysteresis disabled
        0x5E, 0xE0, // Enable right channel AGC, set target level to -20dBFS, hysteresis disabled
        0x00, 0x01, // PAGE 1
        0x3B, 0x00, // Enable Left MICPGA gain and set it to 0dB
        0x3C, 0x00, // Enable Right MICPGA gain and set it to 0dB
        0x00, 0x00, // PAGE 0
        0x59, 0x38, // RA 00h/59h: Set left channel AGC attack time to 480*1 ADC WORD CLOCKs(scale factor 1)
        0x61, 0x38, // RA 00h/61h: Set right channel AGC attack time to 480*1 ADC WORD CLOCKs(scale factor 1)
        0x5A, 0x40, // RA 00h/5Ah: Set left channel AGC decay time to 8704*1 ADC WORD CLOCKs(scale factor 1)
        0x62, 0x40, // RA 00h/62h: Set right channel AGC decay time to 8704*1 ADC WORD CLOCKs(scale factor 1)
        0x51, 0xC2, // Power up both ADC channels. disable soft stepping
        0x52, 0x00, // Unmute both ADC channels
    // clang-format on
};

constexpr std::uint16_t SHOOTER_COMMAND_COUNT{23};
constexpr std::array<std::uint8_t, SHOOTER_COMMAND_COUNT * COMMAND_SIZE> SHOOTER_COMMANDS{
    // clang-format off
        0x00, 0x01, // PAGE 1
        0x0C, 0x08, // HPL routing: LDAC
        0x0D, 0x08, // HPR routing: RDAC
        0x00, 0x00, // PAGE 0
        0x1D, 0x11, // Stereo ADC to Stereo DAC
        0x3F, 0xD6, // DAC power up
        0x40, 0x00, // Unmute both DAC channels
        0x00, 0x01, // PAGE 1
        0x10, 0x16, // HPL is not muted, HPL gain +22dB
        0x11, 0x16, // HPR is not muted, HPR gain +22dB
        0x00, 0x00, // PAGE 0
        0x56, 0xE0, // Enable left channel AGC, set target level to -20dBFS, hysteresis disabled
        0x5E, 0xE0, // Enable right channel AGC, set target level to -20dBFS, hysteresis disable
        0x00, 0x01, // PAGE 1
        0x3B, 0x00, // Enable Left MICPGA gain and set it to 0dB
        0x3C, 0x00, // Enable Right MICPGA gain and set it to 0dB
        0x00, 0x00, // PAGE 0
        0x59, 0x38, // RA 00h/59h: Set left channel AGC attack time to 416*1 ADC WORD CLOCKs(scale factor 1)
        0x61, 0x38, // RA 00h/61h: Set right channel AGC attack time to 416*1 ADC WORD CLOCKs(scale factor 1)
        0x5A, 0x40, // RA 00h/5Ah: Set left channel AGC decay time to 7680*1 ADC WORD CLOCKs(scale factor 1)
        0x62, 0x40, // RA 00h/62h: Set right channel AGC decay time to 7680*1 ADC WORD CLOCKs(scale factor 1)
        0x51, 0xC2, // Power up both ADC channels. disable soft stepping
        0x52, 0x00, // Unmute both ADC channels
    // clang-format on
};

constexpr std::uint16_t AMB_OFF_COMMAND_COUNT{3};
constexpr std::array<std::uint8_t, AMB_OFF_COMMAND_COUNT * COMMAND_SIZE>
    AMB_OFF_COMMANDS{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x10, 0x16, // 2: HPL is not muted, HPL gain +22dB
        0x11, 0x16, // 1: HPR is not muted, HPR gain +22dB
        // clang-format on
    };

constexpr std::uint8_t PLL_ON_HUNTING_COMMAND_COUNT{18};
constexpr std::array<std::uint8_t, PLL_ON_HUNTING_COMMAND_COUNT * COMMAND_SIZE>
    PLL_ON_HUNTING_COMMANDS{
        // clang-format off
        0x00, 0x00, // PAGE 0
        0x1B, 0x00, // BCLK and WCLK - inputs
        0x0C, 0x01, // MDAC divider powered down
        0x13, 0x01, // MADC divider powered down
        0x0B, 0x01, // NDAC divider powered down
        0x12, 0x01, // NADC divider powered down
        0x14, 0x80, // ADC Oversampling rate 128
        0x0D, 0x00, // DAC Oversampling rate 128 (MSB)
        0x0E, 0x80, // DAC Oversampling rate 128 (LSB)
        0x05, 0x92, // PLL ON, P=1, R=2
        0x06, 0x20, // PLL J=32,(D=0)
        0x07, 0x00, // D=0000 (MSB)
        0x08, 0x00, // D=0000 (LSB)
        0x04, 0x07, // PLL_IN=BCLK, CODEC_IN=PLL
        0x0B, 0x82, // NDAC divider powered up, dividing coefficient 2
        0x12, 0x82, // NADC divider powered up, dividing coefficient 2
        0x0C, 0x82, // MDAC divider powered up, dividing coefficient 2
        0x13, 0x82, // MADC divider powered up, dividing coefficient 2
       
        // clang-format on
    };

constexpr std::uint8_t PLL_ON_SHOOTER_COMMAND_COUNT{18};
constexpr std::array<std::uint8_t, PLL_ON_SHOOTER_COMMAND_COUNT * COMMAND_SIZE>
    PLL_ON_SHOOTER_COMMANDS{
        // clang-format off
        0x00, 0x00, // PAGE 0
        0x1B, 0x00, // BCLK and WCLK - inputs
        0x0C, 0x01, // MDAC divider powered down
        0x13, 0x01, // MADC divider powered down
        0x0B, 0x01, // NDAC divider powered down
        0x12, 0x01, // NADC divider powered down
        0x14, 0x80, // ADC Oversampling rate 128
        0x0D, 0x00, // DAC Oversampling rate 128 (MSB)
        0x0E, 0x80, // DAC Oversampling rate 128 (LSB)
        0x05, 0x92, // PLL ON, P=1, R=2
        0x06, 0x20, // PLL J=32,(D=0)
        0x07, 0x00, // D=0000 (MSB)
        0x08, 0x00, // D=0000 (LSB)
        0x04, 0x07, // PLL_IN=BCLK, CODEC_IN=PLL
        0x0B, 0x82, // NDAC divider powered up, dividing coefficient 2
        0x12, 0x82, // NADC divider powered up, dividing coefficient 2
        0x0C, 0x82, // MDAC divider powered up, dividing coefficient 2
        0x13, 0x82, // MADC divider powered up, dividing coefficient 2

        // clang-format on
    };

// ADC fs = 44.1 kHz
// Attack time = 0.015360 => 44.1 kHz * 0.015360 =
// Decay time = 0.2785 s =>
constexpr std::uint16_t HUNTING_BT_STREAM_COMMAND_COUNT{23};
constexpr std::array<std::uint8_t,
                     HUNTING_BT_STREAM_COMMAND_COUNT * COMMAND_SIZE>
    HUNTING_BT_STREAM_COMMANDS{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x0C, 0x0A, // HPL routing: LDAC and MAL
        0x0D, 0x0A, // HPR routing: RDAC and MAR
        0x18, 0x23, // MAL level -20.6dB
        0x19, 0x23, // MAR level -20.6dB
        0x00, 0x00, // PAGE 0
        0x56, 0xE0, // Enable left channel AGC, set target level to -20dBFS, hysteresis disabled
        0x5E, 0xE0, // Enable right channel AGC, set target level to -20dBFS, hysteresis disabled
        0x00, 0x01, // PAGE 1
        0x3B, 0x00, // Enable Left MICPGA gain and set it to 0dB
        0x3C, 0x00, // Enable Right MICPGA gain and set it to 0dB
        0x00, 0x00, // PAGE 0
        0x59, 0x50, // Set left channel AGC attack time to 672*1 ADC WORD CLOCKs(scale factor 1)
        0x61, 0x50, // Set right channel AGC attack time to 672*1 ADC WORD CLOCKs(scale factor 1)
        0x5A, 0x58, // Set left channel AGC decay time to 11776*1 ADC WORD CLOCKs(scale factor 1)
        0x62, 0x58, // Set right channel AGC decay time to 11776*1 ADC WORD CLOCKs(scale factor 1)
        0x3F, 0xD6, // DAC power up
        0x40, 0x00, // Unmute both DAC channels
        0x51, 0xC2, // Power up both ADC channels. disable soft stepping
        0x52, 0x00, // Unmute both ADC channels
        0x00, 0x01, // PAGE 1
        0x11, 0x16, // HPR is not muted, HPR gain +22dB
        0x10, 0x16, // HPL is not muted, HPL gain +22dB
        // clang-format on
    };

constexpr std::uint8_t SHOOTER_BT_STREAM_COMMAND_COUNT{29};
constexpr std::array<std::uint8_t,
                     SHOOTER_BT_STREAM_COMMAND_COUNT * COMMAND_SIZE>
    SHOOTER_BT_STREAM_COMMANDS{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x0C, 0x08, // HPL routing: LDAC
        0x0D, 0x08, // HPR routing: RDAC
        0x00, 0x00, // PAGE 0
        15, 0x01,   // IDAC = 352
        16, 0x60,
        21, 0x01, // IADC = 256
        22, 0x00,
        17, 0x08, // 8x Interpolation
        23, 0x04, // 4x Decimation
        60, 0x00, // DAC prog Mode: miniDSP_A and miniDSP_D NOT powered up together, miniDSP_D used for signal processing
        61, 0x00, // Use miniDSP_A for signal processing
        0x56, 0xE0, // Enable left channel AGC, set target level to -20dBFS, hysteresis disabled
        0x5E, 0xE0, // Enable right channel AGC, set target level to -20dBFS, hysteresis disable
        0x00, 0x01, // PAGE 1
        0x3B, 0x00, // Enable Left MICPGA gain and set it to 0dB
        0x3C, 0x00, // Enable Right MICPGA gain and set it to 0dB
        0x00, 0x00, // PAGE 0
        0x59, 0x38, // RA 00h/59h: Set left channel AGC attack time to 416*1 ADC WORD CLOCKs(scale factor 1)
        0x61, 0x38, // RA 00h/61h: Set right channel AGC attack time to 416*1 ADC WORD CLOCKs(scale factor 1)
        0x5A, 0x40, // RA 00h/5Ah: Set left channel AGC decay time to 7680*1 ADC WORD CLOCKs(scale factor 1)
        0x62, 0x40, // RA 00h/62h: Set right channel AGC decay time to 7680*1 ADC WORD CLOCKs(scale factor 1)
        0x3F, 0xD6, // DAC power up
        0x40, 0x00, // Unmute both DAC channels
        0x51, 0xC2, // Power up both ADC channels. disable soft stepping
        0x52, 0x00, // Unmute both ADC channels
        0x00, 0x01, // PAGE 1
        0x11, 0x16, // HPR is not muted, HPR gain +22dB
        0x10, 0x16, // HPL is not muted, HPL gain +22dB
        // clang-format on
    };

constexpr std::uint16_t AMB_OFF_BT_STREAM_COMMAND_COUNT{19};
constexpr std::array<std::uint8_t,
                     AMB_OFF_BT_STREAM_COMMAND_COUNT * COMMAND_SIZE>
    AMB_OFF_BT_STREAM_COMMANDS{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x0C, 0x08, // HPL routing: LDAC
        0x0D, 0x08, // HPR routing: RDAC
        0x00, 0x00, // PAGE 0
        0x04, 0x07, // PLL_IN=BCLK, CODEC_IN=PLL
        0x05, 0x92, // PLL ON, P=1, R=2
        0x06, 0x04, // PLL J=4,(D=0)
        0x0B, 0x81, // NDAC divider powered up, divding coefficient 1
        0x0C, 0x82, // MDAC divider powered up, dividing coefficient 2
        0x13, 0x82, // MADC divider powered up, dividing coefficient 2
        0x14, 0x80, // ADC Oversampling rate 128
        0x0D, 0x00, // DAC Oversampling rate 128 (MSB)
        0x0E, 0x80, // DAC Oversampling rate 128 (LSB)
        0x1B, 0x00, // BCLK and WCLK - inputs
        0x3F, 0xD6, // DAC power up
        0x40, 0x00, // Unmute both DAC channels
        0x00, 0x01, // PAGE 1
        0x11, 0x16, // 1: HPR is not muted, HPR gain +22dB
        0x10, 0x16, // 2: HPL is not muted, HPL gain +22dB
        // clang-format on
    };

constexpr std::uint8_t BT_PRE_CALL_COMMAND_COUNT{2};
constexpr std::array<std::uint8_t, BT_PRE_CALL_COMMAND_COUNT * COMMAND_SIZE>
    BT_PRE_CALL_COMMANDS{
        // clang-format off
        0x00, 0x00, // PAGE 0
        0x43, 0x80, // Enable headset detection
        // clang-format on
    };

constexpr std::uint8_t BT_CALL_COMMAND_COUNT{25};
constexpr std::array<std::uint8_t, BT_CALL_COMMAND_COUNT * COMMAND_SIZE> BT_CALL_COMMANDS{
    // clang-format off
        0x00, 0x01, // PAGE 1
        0x0C, 0x0A, // HPL routing: LDAC and MAL
        0x0D, 0x0A, // HPR routing: RDAC and MAR
        0x18, 0x27, // MAL level -30.1dB
        0x19, 0x27, // MAR level -30.1dB
        0x00, 0x00, // PAGE 0
        0x56, 0xE0, // Enable left channel AGC, set target level to -20 dBFS, hysteresis disabled
        0x5E, 0xE0, // Enable right channel AGC, set target level to -20 dBFS, hysteresis disabled
        0x1B, 0x00, // BCLK and WCLK - inputs
        0x3F, 0xDA, // DAC power up, right DAC data is routed to left speaker.
        0x40, 0x00, // Unmute both DAC channels
        0x00, 0x01, // PAGE 1
        0x11, 0x16, // HPR is not muted, HPR gain +22dB
        0x10, 0x16, // HPL is not muted, HPL gain +22dB
        0x00, 0x01, // PAGE 1
        0x3B, 0x00, // Enable Left MICPGA gain and set it to 0dB
        0x3C, 0x00, // Enable Right MICPGA gain and set it to 0dB
        0x00, 0x00, // PAGE 0
        0x59, 0x38, // RA 00h/59h: Set left channel AGC attack time to 480*1 ADC WORD CLOCKs(scale factor 1)
        0x61, 0x38, // RA 00h/61h: Set right channel AGC attack time to 480*1 ADC WORD CLOCKs(scale factor 1)
        0x5A, 0x40, // RA 00h/5Ah: Set left channel AGC decay time to 8704*1 ADC WORD CLOCKs(scale factor 1)
        0x62, 0x40, // RA 00h/62h: Set right channel AGC decay time to 8704*1 ADC WORD CLOCKs(scale factor 1)
        0x51, 0xC2, // Power up both ADC channels. disable soft stepping
        0x52, 0x00, // Unmute both ADC channels
        0x43, 0x00, // Disable headset detection
    // clang-format on
};

constexpr std::uint16_t FEEDBACK_ON_COMMAND_COUNT{5};
constexpr std::array<std::uint8_t, FEEDBACK_ON_COMMAND_COUNT * COMMAND_SIZE>
    FEEDBACK_ON_COMMANDS{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x0C, 0x04, // HPL routing: IN1L
        0x0D, 0x04, // HPR routing: IN1R
        0x10, 0x16, // HPL is not muted, HPL gain +22dB
        0x11, 0x16, // HPR is not muted, HPR gain +22dB
        // clang-format on
    };

constexpr std::uint16_t ALL_OFF_COMMAND_COUNT{34};
constexpr std::array<std::uint8_t, ALL_OFF_COMMAND_COUNT * COMMAND_SIZE>
    ALL_OFF_COMMANDS{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x10, 0x56, // 2: HPL muted, gain 0dB
        0x11, 0x56, // 1: HPR muted, gain 0 dB
        0x33, 0x00, // MICBIAS off
        0x18, 0x28, // 3: MAL level mute
        0x19, 0x28, // 4: MAR level mute
        0x00, 0x00, // PAGE 0
        0x40, 0x0C, // 5: Mute both DAC channels
        0x3F, 0x16, // 6: DAC power down
        0x52, 0x88, // 7: Mute both ADC channels
        0x51, 0x00, // 8: Power down both ADC channels.
        0x3C, 0x01, // PRB_P1 DAC signal processing block
        0x3D, 0x08, // PRB_R8 ADC signal processing selected block PRB_R8
        0x1D, 0x01, // No loopback
        0x04, 0x00, // CODEC_IN=MCLK
        0x05, 0x12, // PLL OFF, P=1, R=2
        0x12, 0x01, // NADC divider powered down, divding coefficient 1
        0x0B, 0x81, // NDAC divider powered up, divding coefficient 1
        0x0C, 0x82, // MDAC divider powered up, dividing coefficient 2
        0x13, 0x82, // MADC divider powered up, dividing coefficient 2
        0x14, 0x40, // ADC Oversampling rate 64
        0x0D, 0x00, // DAC Oversampling rate 64 (MSB)
        0x0E, 0x40, // DAC Oversampling rate 64 (LSB)
        0x1B, 0x0C, // BCLK and WCLK - outputs
        0x00, 0x01, // PAGE 1
        0x0C, 0x00, // 9: HPL routing: nothing
        0x0D, 0x00, // 10: HPR routing: nothing
        0x3B, 0x00, // 11: Left MICPGA 0dB
        0x3C, 0x00, // 12: Right MICPGA 0dB
        0x00, 0x00, // PAGE 0
        0x56, 0x00, // 13: Disable left AGC
        0x5E, 0x00, // 14: Disable right AGC
        0x00, 0x01, // PAGE 1
        0x33, 0x50, // MICBIAS on, 1.4V
        // clang-format on
    };

constexpr std::uint16_t ROUTE_AMB_MIC_COMMAND_COUNT{5};
constexpr std::array<std::uint8_t, ROUTE_AMB_MIC_COMMAND_COUNT * COMMAND_SIZE>
    ROUTE_AMB_MIC{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x34, 0x10, // IN2L is routed to Left MICPGA "+" with 20k resistance
        0x36, 0x01, // CM2L is routed to Left MICPGA "-" with 10k resistance
        0x37, 0x10, // IN2R is routed to Right MICPGA "+" with 20k resistance
        0x39, 0x01, // CM2R is routed to Right MICPGA "-" with 10k resistance
        // clang-format on
    };

constexpr std::uint16_t ROUTE_BOOM_MIC_COMMAND_COUNT{5};
constexpr std::array<std::uint8_t, ROUTE_BOOM_MIC_COMMAND_COUNT * COMMAND_SIZE>
    ROUTE_BOOM_MIC{
        // clang-format off
        0x00, 0x01, // PAGE 1
        0x34, 0x04, // IN3L is routed to Left MICPGA "+" with 10k resistance
        0x36, 0x01, // CM2L is routed to Left MICPGA "-" with 10k resistance
        0x37, 0x00, // Nothing is routed to Right MICPGA "+"
        0x39, 0x00, // Nothing is routed to Right MICPGA "-"
        // clang-format on
    };

constexpr std::uint16_t ROUTE_FEEDBACK_COMMAND_COUNT{0};
constexpr std::array<std::uint8_t, ROUTE_FEEDBACK_COMMAND_COUNT * COMMAND_SIZE>
    ROUTE_FEEDBACK{
        // clang-format off
        // clang-format on
    };

// Text "* Sample Rate = 31250"


constexpr std::uint16_t HUNTING_FILTER_COMMAND_COUNT{122};
constexpr std::array<std::uint8_t, HUNTING_FILTER_COMMAND_COUNT * COMMAND_SIZE>
    HUNTING_FILTER_COMMANDS{
        // clang-format off
        0x00, 0x08, // PAGE 8
        // here ADC filter registers
      
    };

// Text "* Sample Rate = 31250"
/
// 0x8A77B6
constexpr std::uint16_t SHOOTER_FILTER_COMMAND_COUNT{122};
constexpr std::array<std::uint8_t, SHOOTER_FILTER_COMMAND_COUNT * COMMAND_SIZE>
    SHOOTER_FILTER_COMMANDS{
        // clang-format off
        0x00, 0x08, // PAGE 8
        // here ADC filter registers

    };

constexpr std::uint16_t CALL_FILTER_COMMAND_COUNT{122};
constexpr std::array<std::uint8_t, CALL_FILTER_COMMAND_COUNT * COMMAND_SIZE>
    CALL_FILTER_COMMANDS{
        // clang-format off
        0x00, 0x08, // PAGE 8
        // here ADC filter registers
  
    };

// DAC filter
// Text "* Sample Rate = 31250"

constexpr std::uint16_t DAC_FILTER_COMMAND_COUNT{95};
constexpr std::array<std::uint8_t, DAC_FILTER_COMMAND_COUNT * COMMAND_SIZE>
    DAC_FILTER_COMMANDS{
        // clang-format off
        // --  DAC filters
        // PRB_P1 is the default
  
    };

// Text "* Sample Rate = 44100"

constexpr std::uint16_t HUNTING_BT_FILTER_COMMAND_COUNT{92};
constexpr std::array<std::uint8_t,
                     HUNTING_BT_FILTER_COMMAND_COUNT * COMMAND_SIZE>
    HUNTING_BT_FILTER_COMMANDS{
        // clang-format off
        0x00, 0x08, // PAGE 8
        // here ADC filter registers

    };

} // namespace dsp_config::bluetooth

We keep the setting in C++ struct and run blocks as needed. (I removed the actual filters to keep the size down in the forum).

When we start the unit and DSP we call power_up and then init.

Then when not using the I2S we call for example:

load_hunting

send_all_off(

THEN_WAIT(10, send_hunting_filter,

THEN(send_route_ambient_mic,

THEN(send_agc_volume,

THEN(send_hunting_settings,

And when switching to mix of analog and I2S:

load_hunting_and_bt_audio

send_all_off(

THEN(send_pll_on_hunting_settings,

THEN_WAIT(30, send_hunting_stream_filter,

THEN(send_dac_filter,

THEN(send_route_ambient_mic,

THEN(send_agc_volume,

THEN(send_dac_volume,

THEN(send_hunting_and_bt_settings,

0 Mir Jeffres 3 months ago in reply to Oskar Brattberg

TI__Genius 17450 points

Hi,

If you can do a register dump from the chip during this AGC-off scenario vs the AGC-on scenario, it will help us diagnose better. However, I would take a look at where you write to registers 0x56 and 0x5e. I see that they are set to enabled for many of your functions in the code, but set to disabled in the all_off_commands list. It looks like you send these first when you enable the I2S, make sure the other commands when you enable I2S eventually enable the AGC as well. Maybe you did not include that code in your enabled I2S commands.

Best,
Mir

0 Oskar Brattberg 3 months ago in reply to Mir Jeffres

Prodigy 55 points

We are setting to do a dump. I will come back with file.

In the meantime, which I tink is important. If we run "send_all_off" twice insted of just once, then the AGC works as expected. But this should not change the resulting registers only the order of them being set.

0 Mir Jeffres 3 months ago in reply to Oskar Brattberg

TI__Genius 17450 points

Hi Oskar,

Can you try adding a software reset to the beginning of your command when you switch? I am having trouble following the scripts order so it will be more obvious what is happening if we have a register dump, or just one long script that you are running to do the configuration. I have a feeling that needing to run one of your functions twice to set the values correctly would be easier to debug if you copied out all the commands in order to see what we are setting. If you are able to make a dump of all commands in order (as well as or instead of the register dump) that would be easier to follow.

Best,
Mir

0 Oskar Brattberg 3 months ago in reply to Mir Jeffres

Prodigy 55 points

Yes that would be one alternative that I asumme work. Do a full intialication every mode change.

This is mem dup of page 0 and 1 during I2s and analog audio.

Fullscreen dsp_mem_dump3.txt Download

dsp mem dump
streaming
page:0x0, addr0x0, val:0x0
page:0x0, addr0x1, val:0x0
page:0x0, addr0x2, val:0x60
page:0x0, addr0x3, val:0x0
page:0x0, addr0x4, val:0x7
page:0x0, addr0x5, val:0x92
page:0x0, addr0x6, val:0x20
page:0x0, addr0x7, val:0x0
page:0x0, addr0x8, val:0x0
page:0x0, addr0x9, val:0x0
page:0x0, addr0xa, val:0x0
page:0x0, addr0xb, val:0x88
page:0x0, addr0xc, val:0x82
page:0x0, addr0xd, val:0x0
page:0x0, addr0xe, val:0x80
page:0x0, addr0xf, val:0x1
page:0x0, addr0x10, val:0x60
page:0x0, addr0x11, val:0x8
page:0x0, addr0x12, val:0x90
page:0x0, addr0x13, val:0x82
page:0x0, addr0x14, val:0x40
page:0x0, addr0x15, val:0x1
page:0x0, addr0x16, val:0x0
page:0x0, addr0x17, val:0x4
page:0x0, addr0x18, val:0x0
page:0x0, addr0x19, val:0x0
page:0x0, addr0x1a, val:0x1
page:0x0, addr0x1b, val:0x0
page:0x0, addr0x1c, val:0x0
page:0x0, addr0x1d, val:0x1
page:0x0, addr0x1e, val:0x81
page:0x0, addr0x1f, val:0x0
page:0x0, addr0x20, val:0x0
page:0x0, addr0x21, val:0x10
page:0x0, addr0x22, val:0x0
page:0x0, addr0x23, val:0x0
page:0x0, addr0x24, val:0x66
page:0x0, addr0x25, val:0xaa
page:0x0, addr0x26, val:0x11
page:0x0, addr0x27, val:0x0
page:0x0, addr0x28, val:0x0
page:0x0, addr0x29, val:0x0
page:0x0, addr0x2a, val:0xe
page:0x0, addr0x2b, val:0x0
page:0x0, addr0x2c, val:0xc0
page:0x0, addr0x2d, val:0x0
page:0x0, addr0x2e, val:0x0
page:0x0, addr0x2f, val:0x0
page:0x0, addr0x30, val:0x0
page:0x0, addr0x31, val:0x0
page:0x0, addr0x32, val:0x0
page:0x0, addr0x33, val:0x0
page:0x0, addr0x34, val:0x0
page:0x0, addr0x35, val:0x12
page:0x0, addr0x36, val:0x2
page:0x0, addr0x37, val:0x2
page:0x0, addr0x38, val:0x2
page:0x0, addr0x39, val:0x0
page:0x0, addr0x3a, val:0x0
page:0x0, addr0x3b, val:0x0
page:0x0, addr0x3c, val:0x1
page:0x0, addr0x3d, val:0x8
page:0x0, addr0x3e, val:0x0
page:0x0, addr0x3f, val:0xd6
page:0x0, addr0x40, val:0x0
page:0x0, addr0x41, val:0xba
page:0x0, addr0x42, val:0xba
page:0x0, addr0x43, val:0x0
page:0x0, addr0x44, val:0x6f
page:0x0, addr0x45, val:0x38
page:0x0, addr0x46, val:0x0
page:0x0, addr0x47, val:0x0
page:0x0, addr0x48, val:0x0
page:0x0, addr0x49, val:0x0
page:0x0, addr0x4a, val:0x0
page:0x0, addr0x4b, val:0xee
page:0x0, addr0x4c, val:0x10
page:0x0, addr0x4d, val:0xd8
page:0x0, addr0x4e, val:0x7e
page:0x0, addr0x4f, val:0xe3
page:0x0, addr0x50, val:0x0
page:0x0, addr0x51, val:0xc2
page:0x0, addr0x52, val:0x0
page:0x0, addr0x53, val:0x0
page:0x0, addr0x54, val:0x0
page:0x0, addr0x55, val:0x0
page:0x0, addr0x56, val:0xe0
page:0x0, addr0x57, val:0x0
page:0x0, addr0x58, val:0x3c
page:0x0, addr0x59, val:0x50
page:0x0, addr0x5a, val:0x58
page:0x0, addr0x5b, val:0x0
page:0x0, addr0x5c, val:0x0
page:0x0, addr0x5d, val:0x3c
page:0x0, addr0x5e, val:0xe0
page:0x0, addr0x5f, val:0x0
page:0x0, addr0x60, val:0x3c
page:0x0, addr0x61, val:0x50
page:0x0, addr0x62, val:0x58
page:0x0, addr0x63, val:0x0
page:0x0, addr0x64, val:0x0
page:0x0, addr0x65, val:0x3c
page:0x0, addr0x66, val:0x0
page:0x0, addr0x67, val:0x0
page:0x0, addr0x68, val:0x0
page:0x0, addr0x69, val:0x0
page:0x0, addr0x6a, val:0x0
page:0x0, addr0x6b, val:0x0
page:0x0, addr0x6c, val:0x0
page:0x0, addr0x6d, val:0x0
page:0x0, addr0x6e, val:0x0
page:0x0, addr0x6f, val:0x0
page:0x0, addr0x70, val:0x0
page:0x0, addr0x71, val:0x0
page:0x0, addr0x72, val:0x0
page:0x0, addr0x73, val:0x0
page:0x0, addr0x74, val:0x0
page:0x0, addr0x75, val:0x0
page:0x0, addr0x76, val:0x0
page:0x0, addr0x77, val:0x0
page:0x0, addr0x78, val:0x0
page:0x0, addr0x79, val:0x0
page:0x0, addr0x7a, val:0x0
page:0x0, addr0x7b, val:0x0
page:0x0, addr0x7c, val:0x0
page:0x0, addr0x7d, val:0x0
page:0x0, addr0x7e, val:0x0
page:0x0, addr0x7f, val:0x0
page:0x1, addr0x0, val:0x1
page:0x1, addr0x1, val:0x8
page:0x1, addr0x2, val:0x51
page:0x1, addr0x3, val:0x0
page:0x1, addr0x4, val:0x0
page:0x1, addr0x5, val:0x0
page:0x1, addr0x6, val:0x0
page:0x1, addr0x7, val:0x0
page:0x1, addr0x8, val:0x0
page:0x1, addr0x9, val:0x33
page:0x1, addr0xa, val:0x40
page:0x1, addr0xb, val:0x10
page:0x1, addr0xc, val:0xa
page:0x1, addr0xd, val:0xa
page:0x1, addr0xe, val:0x0
page:0x1, addr0xf, val:0x0
page:0x1, addr0x10, val:0x16
page:0x1, addr0x11, val:0x16
page:0x1, addr0x12, val:0x40
page:0x1, addr0x13, val:0x40
page:0x1, addr0x14, val:0xcd
page:0x1, addr0x15, val:0x0
page:0x1, addr0x16, val:0x40
page:0x1, addr0x17, val:0x40
page:0x1, addr0x18, val:0x23
page:0x1, addr0x19, val:0x23
page:0x1, addr0x1a, val:0x0
page:0x1, addr0x1b, val:0x0
page:0x1, addr0x1c, val:0x0
page:0x1, addr0x1d, val:0x0
page:0x1, addr0x1e, val:0x0
page:0x1, addr0x1f, val:0x0
page:0x1, addr0x20, val:0x0
page:0x1, addr0x21, val:0x0
page:0x1, addr0x22, val:0x0
page:0x1, addr0x23, val:0x0
page:0x1, addr0x24, val:0x0
page:0x1, addr0x25, val:0x0
page:0x1, addr0x26, val:0x0
page:0x1, addr0x27, val:0x0
page:0x1, addr0x28, val:0x0
page:0x1, addr0x29, val:0x0
page:0x1, addr0x2a, val:0x0
page:0x1, addr0x2b, val:0x0
page:0x1, addr0x2c, val:0x0
page:0x1, addr0x2d, val:0x0
page:0x1, addr0x2e, val:0x0
page:0x1, addr0x2f, val:0x0
page:0x1, addr0x30, val:0x0
page:0x1, addr0x31, val:0x0
page:0x1, addr0x32, val:0x0
page:0x1, addr0x33, val:0x50
page:0x1, addr0x34, val:0x20
page:0x1, addr0x35, val:0x0
page:0x1, addr0x36, val:0x1
page:0x1, addr0x37, val:0x20
page:0x1, addr0x38, val:0x0
page:0x1, addr0x39, val:0x1
page:0x1, addr0x3a, val:0x0
page:0x1, addr0x3b, val:0x0
page:0x1, addr0x3c, val:0x0
page:0x1, addr0x3d, val:0xff
page:0x1, addr0x3e, val:0x0
page:0x1, addr0x3f, val:0xc3
page:0x1, addr0x40, val:0x0
page:0x1, addr0x41, val:0x0
page:0x1, addr0x42, val:0x0
page:0x1, addr0x43, val:0x0
page:0x1, addr0x44, val:0x0
page:0x1, addr0x45, val:0x0
page:0x1, addr0x46, val:0x0
page:0x1, addr0x47, val:0x31
page:0x1, addr0x48, val:0x0
page:0x1, addr0x49, val:0x0
page:0x1, addr0x4a, val:0x0
page:0x1, addr0x4b, val:0x0
page:0x1, addr0x4c, val:0x0
page:0x1, addr0x4d, val:0x0
page:0x1, addr0x4e, val:0x0
page:0x1, addr0x4f, val:0x0
page:0x1, addr0x50, val:0x0
page:0x1, addr0x51, val:0x0
page:0x1, addr0x52, val:0x0
page:0x1, addr0x53, val:0x0
page:0x1, addr0x54, val:0x0
page:0x1, addr0x55, val:0x0
page:0x1, addr0x56, val:0x0
page:0x1, addr0x57, val:0x0
page:0x1, addr0x58, val:0x0
page:0x1, addr0x59, val:0x0
page:0x1, addr0x5a, val:0x0
page:0x1, addr0x5b, val:0x0
page:0x1, addr0x5c, val:0x0
page:0x1, addr0x5d, val:0x0
page:0x1, addr0x5e, val:0x0
page:0x1, addr0x5f, val:0x0
page:0x1, addr0x60, val:0x0
page:0x1, addr0x61, val:0x0
page:0x1, addr0x62, val:0x0
page:0x1, addr0x63, val:0x0
page:0x1, addr0x64, val:0x0
page:0x1, addr0x65, val:0x0
page:0x1, addr0x66, val:0x0
page:0x1, addr0x67, val:0x0
page:0x1, addr0x68, val:0x0
page:0x1, addr0x69, val:0x0
page:0x1, addr0x6a, val:0x0
page:0x1, addr0x6b, val:0x0
page:0x1, addr0x6c, val:0x0
page:0x1, addr0x6d, val:0x0
page:0x1, addr0x6e, val:0x0
page:0x1, addr0x6f, val:0x0
page:0x1, addr0x70, val:0x0
page:0x1, addr0x71, val:0x0
page:0x1, addr0x72, val:0x0
page:0x1, addr0x73, val:0x0
page:0x1, addr0x74, val:0x0
page:0x1, addr0x75, val:0x0
page:0x1, addr0x76, val:0x0
page:0x1, addr0x77, val:0x0
page:0x1, addr0x78, val:0x0
page:0x1, addr0x79, val:0x0
page:0x1, addr0x7a, val:0x0
page:0x1, addr0x7b, val:0x5
page:0x1, addr0x7c, val:0x0
page:0x1, addr0x7d, val:0x0
page:0x1, addr0x7e, val:0x0
page:0x1, addr0x7f, val:0x0

0 Mir Jeffres 3 months ago in reply to Oskar Brattberg

TI__Genius 17450 points

Can you provide a dump during your only analog setup as well? So we can compare between the two. It looks like in this dump that the AGC is on. Here is my commented code for the AGC registers:

0x00 0x56 0xe0 #left agc enabled, target level=-20dBFS, hysteresis is disabled
0x00 0x57 0x00 #left agc noise gate disabled
0x00 0x58 0x3c #l agc maximum gain=30dB
0x00 0x59 0x50 #l agc attack time = 21*32 adc word clocks
0x00 0x5a 0x58 #l agc decay time = 23*512 adc word clocks
0x00 0x5b 0x00 #def debounce time
0x00 0x5c 0x00 #def debounce time
0x00 0x5d 0x3c #l agc gain = 30dB
0x00 0x5e 0xe0 #right agc enabled, target level=-20dBFS, hysteresis is disabled
0x00 0x5f 0x00 #r agc noise gate disabled
0x00 0x60 0x3c #r agc maximum gain=30dB
0x00 0x61 0x50 #r agc attack time = 21*32 adc word clocks
0x00 0x62 0x58 #r agc decay time = 23*512 adc word clocks
0x00 0x63 0x00 #def debounce time
0x00 0x64 0x00 #def debounce time
0x00 0x65 0x3c #r agc gain = 30dB

Best,
Mir

0 Oskar Brattberg 3 months ago in reply to Mir Jeffres

Prodigy 55 points

Fullscreen dsp_mem_dump1.txt Download

dsp mem dump
no streaming, no bt connection
page:0x0, addr0x0, val:0x0
page:0x0, addr0x1, val:0x0
page:0x0, addr0x2, val:0x60
page:0x0, addr0x3, val:0x0
page:0x0, addr0x4, val:0x0
page:0x0, addr0x5, val:0x12
page:0x0, addr0x6, val:0x4
page:0x0, addr0x7, val:0x0
page:0x0, addr0x8, val:0x0
page:0x0, addr0x9, val:0x0
page:0x0, addr0xa, val:0x0
page:0x0, addr0xb, val:0x81
page:0x0, addr0xc, val:0x82
page:0x0, addr0xd, val:0x0
page:0x0, addr0xe, val:0x40
page:0x0, addr0xf, val:0x2
page:0x0, addr0x10, val:0x0
page:0x0, addr0x11, val:0x8
page:0x0, addr0x12, val:0x1
page:0x0, addr0x13, val:0x82
page:0x0, addr0x14, val:0x40
page:0x0, addr0x15, val:0x1
page:0x0, addr0x16, val:0x0
page:0x0, addr0x17, val:0x4
page:0x0, addr0x18, val:0x0
page:0x0, addr0x19, val:0x0
page:0x0, addr0x1a, val:0x1
page:0x0, addr0x1b, val:0xc
page:0x0, addr0x1c, val:0x0
page:0x0, addr0x1d, val:0x1
page:0x0, addr0x1e, val:0x81
page:0x0, addr0x1f, val:0x0
page:0x0, addr0x20, val:0x0
page:0x0, addr0x21, val:0x10
page:0x0, addr0x22, val:0x0
page:0x0, addr0x23, val:0x0
page:0x0, addr0x24, val:0x66
page:0x0, addr0x25, val:0x22
page:0x0, addr0x26, val:0x0
page:0x0, addr0x27, val:0x0
page:0x0, addr0x28, val:0x0
page:0x0, addr0x29, val:0x0
page:0x0, addr0x2a, val:0x0
page:0x0, addr0x2b, val:0x0
page:0x0, addr0x2c, val:0x0
page:0x0, addr0x2d, val:0x0
page:0x0, addr0x2e, val:0x0
page:0x0, addr0x2f, val:0x0
page:0x0, addr0x30, val:0x0
page:0x0, addr0x31, val:0x0
page:0x0, addr0x32, val:0x0
page:0x0, addr0x33, val:0x0
page:0x0, addr0x34, val:0x0
page:0x0, addr0x35, val:0x12
page:0x0, addr0x36, val:0x3
page:0x0, addr0x37, val:0x2
page:0x0, addr0x38, val:0x2
page:0x0, addr0x39, val:0x0
page:0x0, addr0x3a, val:0x0
page:0x0, addr0x3b, val:0x0
page:0x0, addr0x3c, val:0x1
page:0x0, addr0x3d, val:0x8
page:0x0, addr0x3e, val:0x0
page:0x0, addr0x3f, val:0x16
page:0x0, addr0x40, val:0xc
page:0x0, addr0x41, val:0xd0
page:0x0, addr0x42, val:0xd0
page:0x0, addr0x43, val:0x0
page:0x0, addr0x44, val:0x6f
page:0x0, addr0x45, val:0x38
page:0x0, addr0x46, val:0x0
page:0x0, addr0x47, val:0x0
page:0x0, addr0x48, val:0x0
page:0x0, addr0x49, val:0x0
page:0x0, addr0x4a, val:0x0
page:0x0, addr0x4b, val:0xee
page:0x0, addr0x4c, val:0x10
page:0x0, addr0x4d, val:0xd8
page:0x0, addr0x4e, val:0x7e
page:0x0, addr0x4f, val:0xe3
page:0x0, addr0x50, val:0x0
page:0x0, addr0x51, val:0xc2
page:0x0, addr0x52, val:0x0
page:0x0, addr0x53, val:0x0
page:0x0, addr0x54, val:0x0
page:0x0, addr0x55, val:0x0
page:0x0, addr0x56, val:0xe0
page:0x0, addr0x57, val:0x0
page:0x0, addr0x58, val:0x3c
page:0x0, addr0x59, val:0x38
page:0x0, addr0x5a, val:0x40
page:0x0, addr0x5b, val:0x0
page:0x0, addr0x5c, val:0x0
page:0x0, addr0x5d, val:0x3c
page:0x0, addr0x5e, val:0xe0
page:0x0, addr0x5f, val:0x0
page:0x0, addr0x60, val:0x3c
page:0x0, addr0x61, val:0x38
page:0x0, addr0x62, val:0x40
page:0x0, addr0x63, val:0x0
page:0x0, addr0x64, val:0x0
page:0x0, addr0x65, val:0x3c
page:0x0, addr0x66, val:0x0
page:0x0, addr0x67, val:0x0
page:0x0, addr0x68, val:0x0
page:0x0, addr0x69, val:0x0
page:0x0, addr0x6a, val:0x0
page:0x0, addr0x6b, val:0x0
page:0x0, addr0x6c, val:0x0
page:0x0, addr0x6d, val:0x0
page:0x0, addr0x6e, val:0x0
page:0x0, addr0x6f, val:0x0
page:0x0, addr0x70, val:0x0
page:0x0, addr0x71, val:0x0
page:0x0, addr0x72, val:0x0
page:0x0, addr0x73, val:0x0
page:0x0, addr0x74, val:0x0
page:0x0, addr0x75, val:0x0
page:0x0, addr0x76, val:0x0
page:0x0, addr0x77, val:0x0
page:0x0, addr0x78, val:0x0
page:0x0, addr0x79, val:0x0
page:0x0, addr0x7a, val:0x0
page:0x0, addr0x7b, val:0x0
page:0x0, addr0x7c, val:0x0
page:0x0, addr0x7d, val:0x0
page:0x0, addr0x7e, val:0x0
page:0x0, addr0x7f, val:0x0
page:0x1, addr0x0, val:0x1
page:0x1, addr0x1, val:0x8
page:0x1, addr0x2, val:0x51
page:0x1, addr0x3, val:0x0
page:0x1, addr0x4, val:0x0
page:0x1, addr0x5, val:0x0
page:0x1, addr0x6, val:0x0
page:0x1, addr0x7, val:0x0
page:0x1, addr0x8, val:0x0
page:0x1, addr0x9, val:0x33
page:0x1, addr0xa, val:0x40
page:0x1, addr0xb, val:0x10
page:0x1, addr0xc, val:0x2
page:0x1, addr0xd, val:0x2
page:0x1, addr0xe, val:0x0
page:0x1, addr0xf, val:0x0
page:0x1, addr0x10, val:0x16
page:0x1, addr0x11, val:0x16
page:0x1, addr0x12, val:0x40
page:0x1, addr0x13, val:0x40
page:0x1, addr0x14, val:0xcd
page:0x1, addr0x15, val:0x0
page:0x1, addr0x16, val:0x40
page:0x1, addr0x17, val:0x40
page:0x1, addr0x18, val:0x23
page:0x1, addr0x19, val:0x23
page:0x1, addr0x1a, val:0x0
page:0x1, addr0x1b, val:0x0
page:0x1, addr0x1c, val:0x0
page:0x1, addr0x1d, val:0x0
page:0x1, addr0x1e, val:0x0
page:0x1, addr0x1f, val:0x0
page:0x1, addr0x20, val:0x0
page:0x1, addr0x21, val:0x0
page:0x1, addr0x22, val:0x0
page:0x1, addr0x23, val:0x0
page:0x1, addr0x24, val:0x0
page:0x1, addr0x25, val:0x0
page:0x1, addr0x26, val:0x0
page:0x1, addr0x27, val:0x0
page:0x1, addr0x28, val:0x0
page:0x1, addr0x29, val:0x0
page:0x1, addr0x2a, val:0x0
page:0x1, addr0x2b, val:0x0
page:0x1, addr0x2c, val:0x0
page:0x1, addr0x2d, val:0x0
page:0x1, addr0x2e, val:0x0
page:0x1, addr0x2f, val:0x0
page:0x1, addr0x30, val:0x0
page:0x1, addr0x31, val:0x0
page:0x1, addr0x32, val:0x0
page:0x1, addr0x33, val:0x50
page:0x1, addr0x34, val:0x20
page:0x1, addr0x35, val:0x0
page:0x1, addr0x36, val:0x1
page:0x1, addr0x37, val:0x20
page:0x1, addr0x38, val:0x0
page:0x1, addr0x39, val:0x1
page:0x1, addr0x3a, val:0x0
page:0x1, addr0x3b, val:0x0
page:0x1, addr0x3c, val:0x0
page:0x1, addr0x3d, val:0xff
page:0x1, addr0x3e, val:0x0
page:0x1, addr0x3f, val:0xc3
page:0x1, addr0x40, val:0x0
page:0x1, addr0x41, val:0x0
page:0x1, addr0x42, val:0x0
page:0x1, addr0x43, val:0x0
page:0x1, addr0x44, val:0x0
page:0x1, addr0x45, val:0x0
page:0x1, addr0x46, val:0x0
page:0x1, addr0x47, val:0x31
page:0x1, addr0x48, val:0x0
page:0x1, addr0x49, val:0x0
page:0x1, addr0x4a, val:0x0
page:0x1, addr0x4b, val:0x0
page:0x1, addr0x4c, val:0x0
page:0x1, addr0x4d, val:0x0
page:0x1, addr0x4e, val:0x0
page:0x1, addr0x4f, val:0x0
page:0x1, addr0x50, val:0x0
page:0x1, addr0x51, val:0x0
page:0x1, addr0x52, val:0x0
page:0x1, addr0x53, val:0x0
page:0x1, addr0x54, val:0x0
page:0x1, addr0x55, val:0x0
page:0x1, addr0x56, val:0x0
page:0x1, addr0x57, val:0x0
page:0x1, addr0x58, val:0x0
page:0x1, addr0x59, val:0x0
page:0x1, addr0x5a, val:0x0
page:0x1, addr0x5b, val:0x0
page:0x1, addr0x5c, val:0x0
page:0x1, addr0x5d, val:0x0
page:0x1, addr0x5e, val:0x0
page:0x1, addr0x5f, val:0x0
page:0x1, addr0x60, val:0x0
page:0x1, addr0x61, val:0x0
page:0x1, addr0x62, val:0x0
page:0x1, addr0x63, val:0x0
page:0x1, addr0x64, val:0x0
page:0x1, addr0x65, val:0x0
page:0x1, addr0x66, val:0x0
page:0x1, addr0x67, val:0x0
page:0x1, addr0x68, val:0x0
page:0x1, addr0x69, val:0x0
page:0x1, addr0x6a, val:0x0
page:0x1, addr0x6b, val:0x0
page:0x1, addr0x6c, val:0x0
page:0x1, addr0x6d, val:0x0
page:0x1, addr0x6e, val:0x0
page:0x1, addr0x6f, val:0x0
page:0x1, addr0x70, val:0x0
page:0x1, addr0x71, val:0x0
page:0x1, addr0x72, val:0x0
page:0x1, addr0x73, val:0x0
page:0x1, addr0x74, val:0x0
page:0x1, addr0x75, val:0x0
page:0x1, addr0x76, val:0x0
page:0x1, addr0x77, val:0x0
page:0x1, addr0x78, val:0x0
page:0x1, addr0x79, val:0x0
page:0x1, addr0x7a, val:0x0
page:0x1, addr0x7b, val:0x5
page:0x1, addr0x7c, val:0x0
page:0x1, addr0x7d, val:0x0
page:0x1, addr0x7e, val:0x0
page:0x1, addr0x7f, val:0x0

Yes here is an dump when we use only the analog path. The attack and decay has been adjusted for the slightly different Fs.

I understand it would be best to refactor this an switch to a register reset between. But would a register reset, reset all setting LDO CM dsp_a ,soft stepping etc, or should I expects some setting to to remain?

0 Mir Jeffres 3 months ago in reply to Oskar Brattberg

TI__Genius 17450 points

Hi Oskar,

When I had asked about a register reset I was imagining a reset before you run all the new registers for the other configuration. So, your script would look like:

1) reset
2) turn on pll and set input and output
3) special filters or whatever other settings you intend

This way we can guarantee all the same configuration. It looks like AGC is enabled for the most recent dump as well, most differences between the scripts are with the clocks, although I did notice one clocking thing that was weird is in the dump during I2S and analog audio, your IDAC in register 0x10 in page 0 was not a power of 2 so I believe you had set it by mistake. By default, it would be 02 00 starting in register 0x0f, or if you wanted it to be the same as ADC, you could set it to 01 00 so register 0x10 is 00. This affects the DAC processing though, so not necessarily causing your issue. The other thing I noticed was in the I2S+analog audio dump, you had some errors saying there was an overflow in the L and R ADC which may have messed up the operation, making the AGC sound like it wasn't on? Those are my main notes from the register dumps. When you say that the AGC is not working was that confirmed via registers or operation?

Best,
Mir

0 Oskar Brattberg 2 months ago in reply to Mir Jeffres

Prodigy 55 points

We have tested the AGC with signals and measurement, since as you can see the register looks ok. That is also why we started digging into this.

IDAC setting seams to be leftover for previous audio "modes" where we also run the miniDSP. I will reset to default.

The overflow bit could this be related how bring down and up the PLL since the I2S streams continue during this operation?

I will run a test configuration with SW resetan let you know the results.

A sw reset would also reset the LDO and CM settings? So we would have to power those up again and wait for them to settle?

0 Mir Jeffres 2 months ago in reply to Oskar Brattberg

TI__Genius 17450 points

Hi,

Yes, the SW reset would set all registers to their defaults which may change your LDO and CM settings if you had changed them previously. In the application reference guide, there are some example scripts, they show that they start with SW reset and then set all the config for that use case. However if you are able to clean up your code to show each step in order it may help you reveal what may be causing the issue... could you record a step by step of all I2C commands sent? That is, if it would be much less convenient to add in a SW reset in the flow.

Can you describe or show your AGC issue? Maybe the settings changed, or something else? I am not sure I understand the whole problem here.

Best,
Mir

Audio

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TLV320AIC3254: Updating the clock and PLL settings runtime