TAC5112: TAC5112 loopback

Hi Jas,

This is possible, but you need to use the loopback mixer registers as opposed to the INTF_CFG1 register.

To enable ADC1 loopback on DAC1:

Page 0x11, Register 0x5a = 0x40

To enable ADC2 loopback on DAC2:

Page 0x11, Register 0x60 = 0x40

Best,

Garret

Hi Garret, thank you for your speedy response.

Wondering if page 0x11 is valid for 5112, it's not documented in SLASF24A.(Maybe  it's undocumented?)

I tried it anyways for DAC1 but unfortunately didn't see any analogue signal at OUT1P - assuming my DAC configs are correct!
Could you please confirm that page for this codec. If it is absolutely correct I guess my DAC config is incorrect.

Thanks a lot,

Jas

Hi Jas,

Page 0x11 (Page 17) is documented starting on page 214 of SLASF24A.

Your DAC config looks correct - did you make sure the ADC channels are enabled and powered on as well? The snippet you sent only has the DAC channels enabled and powered on.

Also - did you write 0x11 to page 0 to set the page before writing to the page 17 registers?

Best,

Garret

Hi Garret,

sorry for delayed response.

I reverted back to the EV Kit and Purepath3 to try to get both ADC And DAC working together (resorted to USB input on the AC-MB so not our normal AIF/I2S/clocking config). Had some success with this but also have some observations I hope you can help me with.

Tried to use the i2c monitor to read/write to the loopback reg page 0x11, reg 0x5a using the below commands but 1) the loopback did not work, and 2) nothing was read back with the read command. (The read failed if I left out the redundant 00)

w a0 00 11     # Set page to 0x11
w a0 5a 40     # Loopback ADC1 o/p to DAC1 i/p
r a0 5a 00      # Read back reg 5a

The data sheet says the coeff registers seem to want to do multibyte reads (which our MCU implementation can not do). Can the i2c monitor do this and if so what would be the correct write and read commands? I was hoping the i2c monitor would be able to handle without problem.

Failing with the above I fly-wired the Dout to DIn pins on the external ASI header on the AC-MB and this seemed to do the trick temporarily for testing the DAC operation (I saw good replica if the INI1P/M signal at OUT1P/M though there was a bit of crosstalk interference).

Using the PPC preset configs I married together ADC and DAC setups but delayed Enabling the ADC (and obviously the power-up reg) until after both ADC and DAC configs. This sequence was the key going back to our MCU code, as I was setting up the ADC, enable i/p ch and power up ADC, then setting up the DAC, enable o/p ch and power up DAC but retaining the ADC enable and power bits too. This sequence was probably causing the issues I had at the start.

By delaying the Enable and power up of both ADC and DAC till the very end things seemed to work on our application.

However, our application requires we can start and stop both ADC and DAC individually at any time and possibly make setting changes on the fly, so I'd like help knowing what are the permissible sequence of events in allowing this flexibility? Do I need to power-down both ADC and DAC to change config of one of them or is Disabling them enough? Hope you see where I'm coming from.

Going back to the loop back coeff register it would still be useful to know how to read/write to these correctly for our unit-testing, although we are using SPI bus from MCU to codec and so far it's implementation only expects single 8-bit register values, so I'm not sure it can handle multibyte operations.

Many Thanks!

Jas