Part Number: TAC5212
Hello,
I am considering this codec in a new design featuring:
- 1 stereo single-ended AC-coupled line input (2 channels L/R in)
- 4 independant single-ended AC-coupled headphones outputs
- slave mode I2S bus with shared FSYNC/BCLK signals between ADCs and DACs.
- 3 I2S data lines : one for the ADCs' digital output and two for the DACs' digital input (no TDM please)
Q1.
Could you confirm that these requirements can be met using one TAC5212 chip please ?
Q2.
What is the preferred pin to feed this codec with the DAC second digital input line ? (DIN pin being the first one obviously). It is not clear whether GPI1 or GPIOx should be selected.
Q3.
Is any register configuration example available for such a use case ?
Many thanks