How to configure AIC3106 at 8 KHz sampling rate

With this MCLK frequency, you will want to use the PLL. The second set of register values should work (P=2, J.D=14512). Q doesn't matter when using the PLL.

Is the AIC3106 master or slave? Do you see the correct frequency on WCLK?

Thanks for your reply. I have tried enabling the PLL also- still it outputs at the sampling rate of 48KHz and not 8KHz.

I am using the example program, audio_edma_c6747.prj and here they have used the following set up for 48 KHz (the example has been written for 48KHz sampling rate):

    // Configure AIC3106
    EVMC6747_AIC3106_rset(  AIC3106_PAGESELECT, 0 );       // Select page 0
    EVMC6747_AIC3106_rset(  AIC3106_RESET, 0x80 );         // Reset AIC3106

    /* ------------------------------------------------------------------------ *
     *                                                                          *
     *  AIC3106 Setup                                                           *
     *                                                                          *
     *      AIC3106.MCLK = PLL1705.SCK02                                        *
     *      FS = ( AIC3106.MCLK * K ) / ( 2048 * P )                            *
     *                                                                          *
     *      For a FS=[48 kHz] & MCLK=[22.5792 MHz]                              *
     *          : 48kHz = ( 22.5792 MHz * K ) / ( 2048 * P )                    *
     *          : P = 2, K[J.D] = 8.7075                                        *
     *                                                                          *
     * ------------------------------------------------------------------------ */

    // Configure AIC3106 registers
    EVMC6747_AIC3106_rset(  3, 0x22 );  // 5 PLL A                            <- [PLL=OFF][Q=4][P=2]
    EVMC6747_AIC3106_rset(  4, 0x20 );  // 4 PLL B                            <- [J=8]
    EVMC6747_AIC3106_rset(  5, 0x6E );  // 5 PLL C                            <- [D=7075]
    EVMC6747_AIC3106_rset(  6, 0x23 );  // 6 PLL D                            <- [D=7075]

  
    EVMC6747_AIC3106_rset(  7, 0x0A );  // 7 Codec Datapath Setup             <- [FS=48 kHz][LeftDAC=LEFT][RightDAC=RIGHT]
    EVMC6747_AIC3106_rset(  8, 0x00 );  // 8  Audio Interface Control A       <- [BCLK=Slave][MCLK=Slave]
    EVMC6747_AIC3106_rset(  9, 0x00 );  // 9  Audio Interface Control B       <- [I2S mode][16 bit]
    EVMC6747_AIC3106_rset(  10, 0x00);  // 10 Audio Interface Control C       <- [Data offset=0]



    EVMC6747_AIC3106_rset(  15, 0 );    // 15  Left ADC PGA Gain              <- [Mute=OFF]
    EVMC6747_AIC3106_rset(  16, 0 );    // 16 Right ADC PGA Gain              <- [Mute=OFF]
    EVMC6747_AIC3106_rset(  19, 0x04 ); // 19  LINE1L to  Left ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
    EVMC6747_AIC3106_rset(  22, 0x04 ); // 22  LINE1R to Right ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]


    EVMC6747_AIC3106_rset(  27, 0 );    // 27  Left AGC B                     <- [OFF]
    EVMC6747_AIC3106_rset(  30, 0 );    // 30 Right AGC B                     <- [OFF]
    EVMC6747_AIC3106_rset(  37, 0xE0 ); // 37 DAC Power & Output Dvr          <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]
    EVMC6747_AIC3106_rset(  38, 0x10 ); // 38 High Power Output Dvr           <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
    EVMC6747_AIC3106_rset(  43, 0 );    // 43  Left DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
    EVMC6747_AIC3106_rset(  44, 0 );    // 44 Right DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
    EVMC6747_AIC3106_rset(  47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume         <- [Routed]
    EVMC6747_AIC3106_rset(  51, 0x09 ); // 51           HPLOUT Output         <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset(  58, 0 );    // 58           HPLCOM Output         <- []
    EVMC6747_AIC3106_rset(  64, 0x80 ); // 64 DAC_R1 to HPROUT Volume         <- [Routed]
    EVMC6747_AIC3106_rset(  65, 0x09 ); // 65           HPROUT Output         <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset(  72, 0 );    // 72           HPRCOM Output         <- []
    EVMC6747_AIC3106_rset(  82, 0x80 ); // 82 DAC_L1 to LEFT_LOP/M Volume     <- [Routed]
    EVMC6747_AIC3106_rset(  86, 0x09 ); // 83 LINE2R to LEFT_LOP/M Volume     <- []
    EVMC6747_AIC3106_rset(  92, 0x80 ); // 92 DAC_R1 to RIGHT_LOP/M Volume    <- [Routed]
    EVMC6747_AIC3106_rset(  93, 0x09 ); // 93           RIGHT_LOP/M Output    <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset( 101, 0x01 ); // 101 GPIO Control Register B        <- [CODEC_CLKIN = CLKDIV_OUT]
    EVMC6747_AIC3106_rset( 102, 0 );    // 102 Clock Generation Control       <- [PLLCLK_IN and CLKDIV_IN use MCLK]

    // Initialize MCASP1
    mcasp = &MCASP_MODULE_1;

    /* ---------------------------------------------------------------- *
     *                                                                  *
     *  McASP1 is in MASTER mode.                                       *
     *      BCLK & WCLK come from McASP1                                *
     *      DIN is used by write16/write32                              *
     *      DOUT is usec by read16/read32                               *
     *                                                                  *
     * ---------------------------------------------------------------- */

From the above I infer that the person who wrote the example audio_edma_c6747.prj has used McASP1 in master mode and AIC3106 in slave mode. Also BCLK and WCLK comes from McASP

I have used exactly the above except from register 2 to 6 as follows:

    EVMC6747_AIC3106_rset(  2, 0xAA );//48KHz/6=8KHz
    EVMC6747_AIC3106_rset(  3, 0xA2 );  // 5 PLL A                            <- [PLL=ON][Q=2][P=2
    EVMC6747_AIC3106_rset(  4, 0x04);//J=1 for 8KHz
    EVMC6747_AIC3106_rset(  5, 0x46 );  // 5 PLL C                            <- [D=4512]
    EVMC6747_AIC3106_rset(  6, 0x20 );  // 6 PLL D                            <- [D=4512]

I tried enabling PLL and also disabling PLL, but still I cant get it to work. How to check the correct freq on WCLK ?

Also, I cannot enable PLL, because, if I enable PLL, the following conditions need to be met:

(from AIC3106 datasheet page:30)

When the PLL is enabled and D≠0000, the following conditions must be satisfied to meet specified performance:
10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1

Further explanation :

since my PLLCLK_IN=22.5792MHz, my P cannot go greater than 2 (because of the condition: 10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz) , thus, K would be 1.4512 and hence, the conditons below would not be met:

When the PLL is enabled and D≠0000, the following conditions must be satisfied to meet specified performance:
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11

Thats why I cannot enable PLL! is that explanation correct?

I have attached the project herewith for your reference. It is only the audio_edma_c6747 example with changes in only 4 lines in mcasp.c (the place where 8KHz sampling rate is configured instead of 48KHz sampling rate)2211.audio_edma_c6747.zip

I measure the output (transmitting from the codec to the outside world via headphone) frequency using the following method:

I fill the ping buffer fully with 0x7FFFFFFF and pong buffer fully with 0x0 and I use oscilloscope (CRO) and measiure the output square wave in the headphone jack out (connector). The period of one full square wave (positive side +negative side) is 3.3msec for 80 samples. Thus, I infer that sampling rate is 48KHz. No matter what values I use in registers 2 to 6 (that is EVMC6747_AIC3106_rset(  2, to 6)) I get only 3.3ms per period (the ping and pong buffers are 40 words long each- that is 80 samples per transmission)

Thank you for your reply. I tried to use codec as master and McASP as slave, but then, the interrupt service routine was not entered (please see: http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/166754.aspx), so as an alternative method, I tried changing the external audio clock from 24.576MHz to 2.048MHz. I have set the registers such that the WCLK is 8KHz(I measured in the oscilloscope) and the ADC and DAC sampling rate of the codec(AIC3106) are 8KHz. But now, I get white noise+the desired audio signal output in the audio_edma_c6747 example. Also the output audio (which has white noise) is not clear.When I increase the ADC and DAC sampling rate of the codec from 8KHz to 32KHz, I get a more clear audio output(but still it has white noise). Also I observed that the quality of the output audio(but there is still white noise even for 32KHz-quality has improved in the sense, I can clearly hear the words in the audio output when using ADC and DAC sampling rate =32KHz, but I cannot hear the words clearly when using ADC and DAC sampling rate=8KHz. But there is some white noise in all the combinations) increases as I increase the ADC and DAC sampling rate from 8KHz to 16KHz, 24KHz, 32KHz.

Any ideas to get rid of the white noise and get a clear audio output at ADC and DAC sampling rate=8KHz?

I changed the external clock to 2.048MHz by replacing the clock generator chip from 24.576MHz to another 2.048MHz chip

The red font ones are the only changes I have made after replacing the 24 MHz clock crystal chip with 2.048MHz clock crystal chip.

// Configure AIC3106 registers
    EVMC6747_AIC3106_rset(  2, 0xAA );
    EVMC6747_AIC3106_rset(  3, 0x22 );  // 5 PLL A                            <- [PLL=OFF][Q=4][P=2]
    EVMC6747_AIC3106_rset(  4, 0x20 );  // 4 PLL B                            <- [J=8]
    EVMC6747_AIC3106_rset(  5, 0x6E );  // 5 PLL C                            <- [D=7075]
    EVMC6747_AIC3106_rset(  6, 0x23 );  // 6 PLL D                            <- [D=7075]
    EVMC6747_AIC3106_rset(  7, 0x0A );  // 7 Codec Datapath Setup             <- [FS=48 kHz][LeftDAC=LEFT][RightDAC=RIGHT]
    EVMC6747_AIC3106_rset(  8, 0x00 );  // 8  Audio Interface Control A       <- [BCLK=Slave][MCLK=Slave]
    EVMC6747_AIC3106_rset(  9, 0x00 );  // 9  Audio Interface Control B       <- [I2S mode][16 bit]
    EVMC6747_AIC3106_rset(  10, 0x00);  // 10 Audio Interface Control C       <- [Data offset=0]
    EVMC6747_AIC3106_rset(  15, 0 );    // 15  Left ADC PGA Gain              <- [Mute=OFF]
    EVMC6747_AIC3106_rset(  16, 0 );    // 16 Right ADC PGA Gain              <- [Mute=OFF]
    EVMC6747_AIC3106_rset(  19, 0x04 ); // 19  LINE1L to  Left ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
    EVMC6747_AIC3106_rset(  22, 0x04 ); // 22  LINE1R to Right ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
    EVMC6747_AIC3106_rset(  27, 0 );    // 27  Left AGC B                     <- [OFF]
    EVMC6747_AIC3106_rset(  30, 0 );    // 30 Right AGC B                     <- [OFF]
    EVMC6747_AIC3106_rset(  37, 0xE0 ); // 37 DAC Power & Output Dvr          <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]
    EVMC6747_AIC3106_rset(  38, 0x10 ); // 38 High Power Output Dvr           <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
    EVMC6747_AIC3106_rset(  43, 0 );    // 43  Left DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
    EVMC6747_AIC3106_rset(  44, 0 );    // 44 Right DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
    EVMC6747_AIC3106_rset(  47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume         <- [Routed]
    EVMC6747_AIC3106_rset(  51, 0x09 ); // 51           HPLOUT Output         <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset(  58, 0 );    // 58           HPLCOM Output         <- []
    EVMC6747_AIC3106_rset(  64, 0x80 ); // 64 DAC_R1 to HPROUT Volume         <- [Routed]
    EVMC6747_AIC3106_rset(  65, 0x09 ); // 65           HPROUT Output         <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset(  72, 0 );    // 72           HPRCOM Output         <- []
    EVMC6747_AIC3106_rset(  82, 0x80 ); // 82 DAC_L1 to LEFT_LOP/M Volume     <- [Routed]
    EVMC6747_AIC3106_rset(  86, 0x09 ); // 83 LINE2R to LEFT_LOP/M Volume     <- []
    EVMC6747_AIC3106_rset(  92, 0x80 ); // 92 DAC_R1 to RIGHT_LOP/M Volume    <- [Routed]
    EVMC6747_AIC3106_rset(  93, 0x09 ); // 93           RIGHT_LOP/M Output    <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset( 101, 0x01 ); // 101 GPIO Control Register B        <- [CODEC_CLKIN = CLKDIV_OUT]
    EVMC6747_AIC3106_rset( 102, 0 );    // 102 Clock Generation Control       <- [PLLCLK_IN and CLKDIV_IN use MCLK]

    // Initialize MCASP1
    mcasp = &MCASP_MODULE_1;

    /* ---------------------------------------------------------------- *
     *                                                                  *
     *  McASP1 is in MASTER mode.                                       *
     *      BCLK & WCLK come from McASP1                                *
     *      DIN is used by write16/write32                              *
     *      DOUT is usec by read16/read32                               *
     *                                                                  *
     * ---------------------------------------------------------------- */

    mcasp->regs->GBLCTL  = 0;       // Reset
    mcasp->regs->RGBLCTL = 0;       // Reset RX
    mcasp->regs->XGBLCTL = 0;       // Reset TX
    mcasp->regs->PWRDEMU = 1;       // Free-running

    // RX
    mcasp->regs->RMASK      = 0xffffffff; // No padding used
    mcasp->regs->RFMT       = 0x00018078; // MSB 16bit, 1-delay, no pad, CFGBus
    mcasp->regs->AFSRCTL    = 0x00000112; // 2TDM, 1bit Rising, INTERNAL FS, word
    mcasp->regs->ACLKRCTL   = 0x000000A7; // Rising INTERNAL CLK,(from tx side)
    mcasp->regs->AHCLKRCTL  = 0x00000000; // INT CLK (from tx side)
    mcasp->regs->RTDM       = 0x00000003; // Slots 0,1
    mcasp->regs->RINTCTL    = 0x00000000; // Not used
    mcasp->regs->RCLKCHK    = 0x00FF0008; // 255-MAX 0-MIN, div-by-256

    // TX
    mcasp->regs->XMASK      = 0xffffffff; // No padding used
    mcasp->regs->XFMT       = 0x00018078; // MSB 16bit, 1-delay, no pad, CFGBus
    mcasp->regs->AFSXCTL    = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word
    mcasp->regs->ACLKXCTL   = 0x000000A7; // ASYNC, Rising INTERNAL CLK, div-by-16
    mcasp->regs->AHCLKXCTL  = 0x00000000; // EXT CLK
    mcasp->regs->XTDM       = 0x00000003; // Slots 0,1
    mcasp->regs->XINTCTL    = 0x00000000; // Not used
    mcasp->regs->XCLKCHK    = 0x00FF0008; // 255-MAX 0-MIN, div-by-256

    mcasp->regs->SRCTL5     = 0x000D;     // MCASP1.AXR1[5] --> DIN
    mcasp->regs->SRCTL0     = 0x000E;     // MCASP1.AXR1[0] <-- DOUT
    mcasp->regs->PFUNC      = 0;          // All MCASPs
    mcasp->regs->PDIR       = 0x14000020; // All inputs except AXR0[5], ACLKX1, AFSX1

    mcasp->regs->DITCTL     = 0x00000000; // Not used
    mcasp->regs->DLBCTL     = 0x00000000; // Not used
    mcasp->regs->AMUTE      = 0x00000000; // Not used

    // Starting sections of the McASP
    mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON;                                    // HS Clk
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );  
    mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON;                                    // HS Clk
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );
   
    mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON;                                     // Clk
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );
    mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON;                                     // Clk
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );

    mcasp->regs->XSTAT = 0x0000ffff;        // Clear all
    mcasp->regs->RSTAT = 0x0000ffff;        // Clear all

    mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON;                                      // Serialize
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );
    mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON;                                      // Serialize
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );

    // Write a 0, so that no underrun occurs after releasing the state machine
    mcasp->regs->XBUF5 = 0;
    mcasp->regs->RBUF0 = 0;

    mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON;                                       // State Machine
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
    mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON;                                       // State Machine
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );

    mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON;                                        // Frame Sync
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
    mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON;                                        // Frame Sync
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );
}

The white noise went away after I used the following values:

    // Configure AIC3106 registers
    EVMC6747_AIC3106_rset(  2, 0xAA );
    EVMC6747_AIC3106_rset(  3, 0x11);//0x22 );  // 5 PLL A                            <- [PLL=OFF][Q=4][P=2]
    EVMC6747_AIC3106_rset(  4, 0xC0);//0x20 );  // 4 PLL B                            <- [J=8]
    EVMC6747_AIC3106_rset(  5, 0x0);//0x6E );  // 5 PLL C                            <- [D=7075]
    EVMC6747_AIC3106_rset(  6, 0x0);//0x23 );  // 6 PLL D                            <- [D=7075]

The above means, I have configured WCLK of McASP = 2.048MHz, so MCLK of codec = 2.048KHz, P=1, K=48,J=48,D=0,R=1.Using these values Fsref=48KHz. The only problem is Q. I dont enable Q. So, I have to configure the correct value for Q. Q=CLKDIV_IN/(Fsref*128) = 2048000/(48000 * 128)=0.3333, unfortunately Q can neither be set to 0 nor to 0.333, not even 1.

What should be the value of Q?

But the audio output still sounds like coming from a deep well!

Sorry about the unclean version of code in last post. Here is a cleaner version:

    // Configure AIC3106 registers
    EVMC6747_AIC3106_rset(  2, 0xAA );//Fsref/6=8KHz
    EVMC6747_AIC3106_rset(  3, 0x11);  // 5 PLL A                            <- [PLL=OFF][Q=2][P=1]
    EVMC6747_AIC3106_rset(  4, 0xC0);  // 4 PLL B                            <- [J=48]
    EVMC6747_AIC3106_rset(  5, 0x0);  // 5 PLL C                            <- [D=0]
    EVMC6747_AIC3106_rset(  6, 0x0);  // 6 PLL D                            <- [D=0]