The PCM4222 includes two active-high digital overflow outputs, OVFL (pin 37) and OVFR (pin 38), corresponding to the left and right channels, respectively. These outputs are functional when the PCM output mode is enabled, as the overflow detection circuitry is incorporated into the digital filter engine. The overflow indicators are forced high whenever a digital overflow is detected for a given channel. The overflow indicators may be utilized as clipping flags, and monitored using a host processor or light-emitting diode (LED) indicators.
I have a few queries regarding that.
1. Need to know the relationship of OVFL and OVFR bits with respect to. the PCM timing diagram. The Datasheet only gives this functional description, no timing info.
2. Circuit is PCM1792 driving a PGA2320.
Regarding the PGA, the customer is using a digital pot for the ramping-down of the DAC output from full scale to 0.
Is there any digital pot available with more than 1000 steps ?
The PGA2320 has a dynamic range of 100dB. The DAC ( PCM1792A) has a dynamic range of 120dB >. So just by suing the PGA , we lose 20 dB of dynamic range.
Do we have any other product ( PGA) or solution for this problem ?
