[Urgent]Confirm the register which is generated by PurePathStudio

Kaka:

When loading a series of cfg commands it may be desirable or necessary to incorporate a delay between commands such as following the configuration of a PLL.  Before submitting subsequent cfg commands the PLL may need to lock in order for the device to correctly read the commands.  This register [0][254] is provided to generate delays measured in ms.  i.e.

/            # reg[  0][254] = 0x0a    ; Delay 10ms for PLL to lock
   {254,0x0A},

This command writes "0x0A" to the register [0][245] causing a 10 ms delay before the next command is read thus allowing the PLL to lock. 

Best Regards,

BAK

Kaka,

Actually there is an error in this script. It should actually be changed from...

/            # reg[  0][254] = 0x0a    ; Delay 10ms for PLL to lock
   {254,0x0A},

to...

/            # reg[254][  0] = 0x0a    ; Delay 10ms for PLL to lock
   {254,0x0A},

Otherwise, PurePath will try to write to this register that does not exist through I2C.

Regards,

J-

Kaka,

This is not a register in the actual device. Setting page 254 basically tells PurePath to implement a delay.

The docuentation that explains this is in the PurePath extranet.

 Here is an example:

SystemSettingsCode (delay 5ms):

reg[254][  0] = 0x05;

Output .cfg file:

d 5

Output .h file (you would need to tell MCU to interpret 254 as a delay, 255 as jump to c-ram, i-ram):

{254, 5}

Regards,

J-