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No signals out of PCM4222

Bob Stadtherr
Prodigy 20 points
Other Parts Discussed in Thread: PCM4222

Trying to debug a new design using PCM4222. Used in master mode (S/M=0). Not getting any signals on BCK,LRCK or Data out or the DSD signals. PCMEN and DSDEN are high, MODEN is low. MCKI is present from my system at 11.2896MHz. Power supplies look good and I am getting the expected voltage on the VCOM pins.

Data sheet does not mention anything about power supply sequencing... is there any requirements here? VCC (4V) is derived from a linear regulator, while VDD (3.3V) is derived from a switching regulator. So I'm fairly certain VDD comes up shortly AFTER VCC. I don't see anything that says this could be a problem. I'm searching for any ideas on why chip appears to be mostly dead.

Thanks

  • 0
    TI__Guru**** 189401 points

    Hi, Bob,

    Welcome to e2e, and thank you for your interest in our devices!

    I don't see anything obvious here... Let me see if any of my colleagues have any ideas...

    -d2

  • 0 in reply to Don Dapkus
    Prodigy 20 points

    Hi Don,

    I think I made a breakthrough yesterday. Not too surprisingly it has to do with the M/S pin. In my design I have that pin driven low by a CPLD. (all the signals pass through the CPLD and that would give me the option of making the CPLD clock master) Anyway there was some strange behavior on that pin from the CPLD, and as soon as I would probe that net with a meter or scope it would snap low and the A/D would start to output signals. I'm not fully understanding how a CPLD pin declared to be always 0 is doing what it is, but a 10K pull down seems to have cleared up the symptoms.

  • 0 in reply to Bob Stadtherr
    TI__Genius 12255 points

    Hi Bob:

                 If you set the CPLD pin is zero, the output will be low level. You can disconnect the PCM4222's S/M pin to test the CPLD's output to see the low level value.You should be careful that  the CPLD 's pin the output level can be changed, it has TTL,LVTTL,LVCMOS and so on. The low level is different in the different level.

                   

  • 0 in reply to Derek Xie
    TI__Genius 12255 points

    Hi Bob:

    By the way, the CPLD's softwae like altera is QuartusII and the Xilinx is ISE, it can set the output pin to pull-up,pull-down and Tri-state. You can try to set in the CPLD's software so that you can remove the outside resistor.