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what is the sequence for powering down/up the AIC33

Shlomo Kabaz
Intellectual 690 points

We  are  using  the AIC33 as a master  in our project .

The  input lines we use are :  line2_LP and  line1_LP

The output lines  we use     :  MONO_LOP ,  LEFT_LOP  (Single ended )

When  we  take the  AIC33 from power  down  to  high  somtimes  there  is no output in one of the output lines , but the digital input is good .

Also the SPI  line  works well  ( like the spec says ) .

When we read  the register  79  MONO_LOP , we  get in D1 bit  value  '1'  ( Not all programmed gains to MONO_LOP/M have been applied yet ) , why is that .

Is there a robust sequence for entering and  leaving Low power for this device ?

Regards , Shlomo  Kabaz .

 

 

 

  • 0
    TI__Mastermind 28585 points

    In order for the "Alll programmed gains have been applied" flag to work correctly, the specific output channel must be fully routed to the DAC and powered up. The purpose of this flag is to let the user know that the target gain level has been reached when using soft-stepping. 

    A good sequence for powering down is:

    1. Mute the DAC/ADC's

    2. Mute the outputs

    3. unroute and power down the outputs

    4. power down the DAC/ADC

    5. power down the PLL

    When powering up, the opposite sequence would be used.

  • 0 in reply to Converter Apps
    Intellectual 690 points

    Thank  you  very much , this has helped  us A LOT ,

    but  , it seems that the problem  ocuurs less but is still there .

    We did not manage to do a proper sequence  that will  leave the  "Alll programmed gains have been applied"  cleared '0' !!!

    The following code is the sequence in our ti5510  dsp (we are Not using the PLL):

    void waitNop(int num)

    {  int  i;

     for(i=0 ; i< num; i++)   

      asm(" NOP ");

    }

    void  softStepUpMonoLop(void)

    {  int  i;

     for(i=120 ; i >= 0 ; i--) {   

       setReg(75, (0x80 | i) );  

     }

    }

    void  softStepDownMonoLop(void)

    {  int  i;

     for(i=0 ; i < 120 ; i++) {  

         setReg(75,(0x80 | i));

      }

    }

    void  new_powerDownAic33(void)

    {

      /* Register 9 : Re-Sync Mute Behavior ??? */

      setReg(7,0x00);

      softStepDownMonoLop();    

      /* 1. Mute the DAC/ADC's */     

      setReg(15,0x80); // Register 15: Left ADC PGA Mute         

      waitNop(800);  

      setReg(16,0x80); // Register 16: Right ADC PGA Mute    

      waitNop(800);  

      setReg(43,0x80); // Register 43: Left DAC Digital Mute     

      waitNop(800);  

      setReg(44,0x80); // Register 44: Right DAC Digital Mute    

      waitNop(800);

      /* 2. Mute the outputs */  

       setReg(79,0x01); // Mute MONO_LOP    

       waitNop(800);  

       setReg(86,0x01); // Mute LEFT_LOP    

       waitNop(800);

       /* 3. Unroute and power down the outputs*/  

       setReg(75,0x77); // unRoute DAC_L1 from  MONO_LOP/M    

       waitNop(800);  

       setReg(85,0x00); // unRoute DAC_R1 from  LEFT_LOP/M  

       waitNop(800);  

       setReg(79,0x00); // Power Down MONO_LOP

       waitNop(800);    

       setReg(86,0x00); // Power Down LEFT_LOP  

       /* 4. power down the DAC/ADC */  

       setReg(19,0x78); // Left  ADC channel is powered down         

       waitNop(800);    

        setReg(22,0x78); // Right ADC channel is powered down     

        waitNop(800);

        setReg(37,0x00); // Right DAC and left DAC powered down */

         waitNop(800);

    }

     

    void  new_powerUpAic33(void)

    {

     setReg(37,0xC0);  

     waitNop(200);

     setReg(19,0x7C);

     waitNop(200);

     setReg(22,0x7C);

     waitNop(200);

     setReg(79,0x01); // Power Up MONO_LOP

     waitNop(200);  

     setReg(86,0x01); // Power Up LEFT_LOP

     waitNop(200);

     softStepUpMonoLop();

     // setReg(75,0x80); // Route DAC_L1 to MONO_LOP/M

     setReg(85,0x80); // Route DAC_R1 to LEFT_LOP/M

     waitNop(200);

     setReg(79,0x09); // un mute MONO_LOP

     waitNop(200);

      setReg(86,0x09); // un mute LEFT_LOP

      setReg(15,0x00); // Register 15: Left ADC PGA Mute  

      waitNop(200);

      setReg(16,0x00); // Register 16: Right ADC PGA Mute  

      waitNop(200);

      setReg(43,0x00); // Register 43: Left DAC Digital Mute

      waitNop(200);

      setReg(44,0x00); // Register 44: Right DAC Digital Mute

      waitNop(200);  

      setReg(7,0x0A);

    }

     

    Regards .

     

     

     

     

     

  • 0 in reply to Shlomo Kabaz
    TI__Mastermind 28585 points

    If you do the read at the very end of your setup, it should work. The DAC path must be completely routed including Register 7. there can also be some issues if the path is partially unrouted then rerouted. At this point, even though the path is properly routed, the flag might not set. The internal flag logic expects to be fully routed, then fully unrouted to always work reliably. 

    Either way, unless you are doing a long mute where you want to make sure the mute is fully applied before stopping a file or turning off the output, it is not critical that this flag be correct. You can also just use a set delay to insure that gains have had time to soft-step. Even if the flag becomes confused, the device will function. If you need the flag and it is not correct, you would have to do a reset and insure that the expected sequence is always met.