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SRC4192 MCLK, BCLK setting issue

Edwin Ng
Intellectual 980 points
Other Parts Discussed in Thread: SRC4192, PLL1705

Dear Sir

 i have tested SRC4192 evaluation board and get below observation

 Setting

 1. 16bit 44.1K signal input from SPDIF to CS8414 BCLK, data, LRCLK to SRC4192

 2.SRC4192 clock source by PLL1705 with 24.576MHz

 3. SRC4192 output I2S format,

 4. Mode setting of SRC4192 is "Output Port is in Master mode with RCKI = 128fs"

 Observation

 1. The LRCLK output of SRC4192 is 192KHz

 2. The BCLk output of SRC4192 is 12.288MHz (suppose 6.144MHz)

 3. Some Data output from SRC4192  data pin even physically disconnect SPDIF input

 My observation is unexpected, what's the problem?

My question is

1. Why SRC4192 output BCLK is 12.288MHz? suppose 16bit x2 x 192K=6.144MHz

2. Why SRC24192 dout pin have many signal output? even I disconnected the SPDIF input from CS8414

3. The output sampling rate is fixed eg.192K, even input 32K, 44.1K, 48K, the output sample frequency is fix, is it correct?

 BR

 Edwin