Greetings,
I am experimenting with the DSD1792A audio DAC connected to an FPGA. I can get reasonable-looking output in the external digital filter mode, but not in internal digital filter mode. I don't understand what is happening, but I imagine it has something to do with the input format or the configuration of the digital filter. It would be helpful if someone experienced with this part could help diagnose the mistakes in my setup.
Operating conditions are:
- 11.2896 MHz system clock
- 44.1 kHz audio sample rate
- 24-bit I2S format stereo PCM data; BCK at 64x Fs
I'm not sure how to describe the issue other than that the output amplitude is much reduced and doesn't cover the entire sample period. For example, this is the I2S input for a full amplitude squarewave at Fs/2 (samples alternate between 0x800000 and 0x7FFFFF):
Here is the output waveform for that stimulus:
(My apologies for the messy trace, this was taken with a 30 ohm resistor for I/V conversion.)
The initial (negative) pulses at 1/Fs are present at all times, and the brief smaller pulses appear to be in proportion to the desired signal.
I experimented with different input formats and found the behavior to be consistent between right-justified, I2S and left-justified.
I can read and write registers using the SPI interface, but not all of the registers have the expected effect on the output. The mute and attenuator features don't seem to do anything, for example. (This is true in either internal or external digital filter mode.) Some other registers work fine, like output phase reversal and delta-sigma oversampling ratio. What do you make of this?
Thanks
Michael
