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Inquiry regarding TLV320AIC3101 system configuration

Atsushi Okui
Genius 4015 points
Other Parts Discussed in Thread: TLV320AIC3101

Hello, all

Now we are designing our system with TLV320AIC3101, then have some issue on our system configuration.

Please see the enclosed report and feedback us with your comment.

2021.Inquiry regarding AIC3101 system configuration.doc

We thank you in advance for your information.

Best regards,

  • 0
    TI__Mastermind 28585 points

    Okui-san,

    I will investigate this issue and get back to you shortly.

    Is it possible to forward a higher resolution schematic? The current schematic is a little bit hard to read.

  • 0 in reply to Converter Apps
    Genius 4015 points

    Hello, thank you for your confirmation towards the inquiry regarding AIC3101.

    Unfortunately, this full schematic should not be disclosed on web since some circuit includes confidential information.

    Meanwhile, I could observe this same phenomenon on AIC3101EVM. 

    I also tested to use several value of resistor in front of IN2L.

    Please refer to enclosed test report, which also shows some configuration on EVM, and feedback us with your comment.

    We thank you once again for your information.

    Best regards,

    6013.Test report of IN2RL on AIC3101EVM.doc

  • 0 in reply to Atsushi Okui
    TI__Mastermind 28585 points

    The issue is that by default, all unused inputs are floating and will drift to 0 volts. Since the inputs are AC coupled, if a signal is still present when the input is turned off, then on the AIC3101 side of the input AC coupling cap which is now biased at 0 volts, the signal will go above and bellow ground which will violate the input range.

    If a signal is going to be present when an input is not routed to the ADC, you must set a weak common mode voltage at the unused inputs. On Page 0, Register 20 and 23 are listed as reserved, however, if you send a 0x7C to both Register 20 and 23, you will see that the inputs will be biased to mid-rail even when not routed.

    The only values you should send to Register 20 and 23 are:

    0x78 = Unused inputs will be Hi-Z

    0x7C= Unused inputs will be weakly driven to mid-rail

  • 0 in reply to Converter Apps
    Genius 4015 points

    Hello, thank you for your previous support on IN2R/L signal dropped issue.

    We are now setting the register 20 and 23 in accordance with your suggestion.

    On this configuration, I found some noise which is effected by IN2R/L input which is not set to input into AIC3101 by its register setting.

    When applied low amplitude signal into IN2R/L, this effect is not viewed clearly.

    5076.TEK00002.TIF

    However when increasing this amplitude, this effect is viewed more clear than above situation.

    7725.TEK00001.TIF

    Please let us clarify how we could remove this effect completely.

    We thank you once again for your information.

    Best regards,

  • 0 in reply to Atsushi Okui
    TI__Mastermind 28585 points

    Hi,

    This is probably do to cross talk. The cross talk (input channel separation) spec is given on page 7 of the datasheet. Although we only give IN1L/R spec, it would be similar between In1 and In2. If greater separation is needed, you would have to use an external switch. If you are seeing more cross talk than expected, layout can be an issue. Check for proper spacing between traces.

  • 0 in reply to Converter Apps
    Genius 4015 points

    Hello, thank you for your reply on previous inquiries.

    After our internal discussion, we decided to use external pull-up/down resistance to keep input bias level higher than absolute maximum ratings.

    On this configuration, we would like to know about the internal impedance on AIC3101 when PGA Gain=0dB.

    The enclosed diagram is actual input design on LINE2L and LINE2R, when both lines are connecting into AIC3101 internally.

    On this configuration, we assume that input resistance when PGA Gain=0dB is 20kohm, as described on page 7 of the datasheet, and the DC voltage on point A should be 1.5V which is calculated based on internal bias voltage on AIC3101 is 2.96V/2=1.48V

    However, when measuring point A on actual system, the measured voltage is 1.42V.

    We assume that other internal resistance, for example in ADC core on AIC3101, need to be taken in consideration to lead accurate bias voltage.

    Please let us clarify how to reach accurate bias voltage on our configuration.

    We thank you once again for your information.

    Best regards,

  • 0 in reply to Atsushi Okui
    TI__Mastermind 28585 points

    Hi,

    The input common mode voltage is 1.35V and is generated by a band gap reference, so it will stay fairly fixed even with a change in Avdd.

    In spite of the nominal value of the input common mode voltage, it is not tested or trimmed so it can vary from device to device. 

    The input impedance is 20 k Ohm with 0 dB of gain on the front end. It can vary +/- 20%.