AIC34_Sync_Mics

Hi, Mushtag,

Sorry we missed your post; I've asked Dave to respond.

-d2

Hi Mushtaq.

Here is a good app note on getting the codecs sync'ed.This was written for the ADC3101 which has a slightly different register map, however the basic concept is the same. Let me know if you have any questions.

http://www.ti.com/lit/an/slaa508/slaa508.pdf

Hi:

Thanks a lot!

I went through the application note. It uses TDM. Is this necessary? Can't it be done with I2S?

Thanks a lot!

Cheers,

Mushtaq

Hi:

I have some more questions. The application note uses TLV320ADC3101 as an example. The chip has a register to power up the NADC divider. Powering up and loading the divider causes all the codecs in the chain to receive clocks; however, on the AIC34 there is no such register. by default fs(ref)=48K on the AIC34. What should we use as the equivalent on the AIC34?

Thanks a lot!

Cheers,

Mushtaq

Yeah, the AIC34 doesn't have that feature. Fortunately, it is not required. How are your devices configured. Is one master and one slave or are both slaves? Are you using MCLK on both A and B?

The easiest way to configure these will depend on the answers.

Hi:

Yes, Sir. Codec A is the master and Codec B the slave. We do use MCLK on both. BCLK and WCLK from A are routed to B. MCLK of 19.2MHz is common, from an external source. I can send the schematic if necessary. You local representation has it.

Thanks a lot!

Cheers,

Mushtaq

If you have the ability to turn MCLK off and on, it might be easier to just hold off the MCLK until everything is programmed and ready to go, then supply MCLK which should get everything sync'ed.

Sir:

I have no control over MCLK!

Isn't there anything within the codec that I can program to trigger the clocks?

Thanks a lot!

Cheers,

Mushtaq

I think you need to find a way to gate the MCLK. The problem is that once the MCLK is running, there is no way to simultaneously turn on all of the converters. Since the converters are powered up through individual registers and the I2C sequence will happen serially, each converter will sync to MCLK at a different time. Alternatively, you could have the master block set to look at GPIO2 for clocking (where hopefully, there is nothing there). Next you could send block B the MCLK from the Block A GPIO1 (where still there would be nothing). Next set up both devices such that they are ready to go, then switch Block A to look for MCLK on MCLK. At this point MCLK would hit the converters and be output on GPIO1 such that Block B would also sync. This involves a hardware change to source MCLK on Block B via GPIO1 on Block A.

Perhaps just adding a gate on MCLK would be easier. 

Hi:

Thanks a lot!

Your alternative solution using GPIO2 and GPIO1 will not work for us, as this requires the PLL to be disabled, and in the non-PLL mode we cannot achieve 8KH exaclty.

Looks like we will have to gate MCLK.

Thanks a lot!

Cheers,

Mushtaq

Hi:

Since we have BCLK and WCLK outputs from codec A already hooked up to BCLK and WCLK of codec B, what do you think of the following procedure for synchronizing the two? Could you please review it and give us feedback?

Thanksa lot!

Cheers,

Mushtaq

#######################################################################
Codec A - Master Mode
MCLK Source - MCLK(19.2MHZ)
fsref - 48000HZ
WCLK (fs) - 8000HZ
BCLK - 256*fs =2.048 MHZ
PLL - Enabled
MCLK(MHz) P R J D ACHIEVEDfS(ref)  % ERROR
19.2  1 1 5 1200 48000.00  0.0000

#########################################################################
Codec B - Slave Mode
MCLK Source - BCLK from Codec A(2.048MHZ)
fsref - 48000HZ
WCLK (fs) - 8000HZ
BCLK = 2.048 MHZ from Codec A
PLL - Enable to produce fsref 256*48000HZ from 2.048 MHZ
MCLK (MHz) P  R J D ACHIEVEDfS(ref)  % ERROR
2.048  1 1 48 0 48000.00  0.0000
##########################################################################

Steps to Sychronize both Codec A and Codec B

Step 1 - Configure CodecA to look at GPIO2 and CodecB to look at BCLK. At this point there are no clocks for both Codec A and Codec
Step 2 - Place DOUT of both CodecA and CodecB in high-impedance state when valid data is not being sent
Step 3 - Configure the Codec A PLL Values and enable the PLL for 19.2MHZ
Step 4 - Configure the Codec B PLL Values and enable the PLL for 2.048 MHZ
Step 5 - Configure the Codec A and Codec B into DSP mode
Step 5 - Configure the CodecA to look at MCLK Pin . At this point the CodecA will have MCLK - 19.2 MHZ and CodecB will have 2.048MHZ

To insure sync between block a and block b, I think the same MCLK should go to both. By using two different PLL settings, there is a possibility that the channels will lock at different times. I think the sequence looks good, but it would be better if the PLLs were using the same clock.