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PCM1870A-The Max clk can be supply in BCK pin in slave mode

Other Parts Discussed in Thread: PCM1870A, OMAPL138, TLV320ADC3101, TLV320AIC3106, PCM1870

Hi,

for my new design I am using PCM1870A for converting stereo microphone to 16bit TDM.

I config the ADC to be in slave mode.

I provide the signals for the ADC from external CPU (OMAPL138). 

The TDM should be with the following configuration:

-The SCKI (F2 pin) pin should be at 12.288Mz.

-The LRCK (E1 pin) pin should be at 48KHz (FS).

-The BCK (F1 pin)  pin should be at 12.288Mz.

According to the datasheet I am should be able to provide the following signals frequency but I want to confirm my design.

So my question is this:

Can I provide to BCK pin clock with 12.288MHz frequency in Audio TDM format (When the ADC config to be in Slave mode)?

I'd appreciate a quick answer.

Thanks in advance,

Itamar

  • Hi, Itamar,

    I've asked my colleague to look into this for you.

    -d2

  • Hi Itamar,

    Well, I'm interested to know why you are trying to use Audio TDM format. TDM (Time Division Multiplexing) is usually used in applications where there is more than 2 channels. Commonly, I2S, left (PCM) or right justified, would be used in a stereo (2 channel) application.

    The PCM1870A does not support Audio TDM format. Where do you see this in the d/s?

    We have other parts that use TDM, like the TLV320ADC3101, but I don't think it is necessary for your situation.

    Regards,

    ~John 

  • Hi,

    Actually On my board I have 8 PCM1870A to support 16 Line-In inputs.

    I work with the PCM1870A in DSP mode (Also call TDM format) (In SLAVE mode).

    Between the PCM1870A devices and the OMAPL138 I have a CPLD that from the ADC side recieve 8 streams of 32bit (each ADC sent back 2 CH of 16 bit, so from each ADC the CPLD recieve 32bit).

    The CPLD sum all this 8 streams to one TDM signal with 256bit (32bitX8channels=256bits) to OMAPL138 to McASP bus interface.

    Acoording to PCM1870A datasheet ,page 18 on the bootom of the page, see (e) DSP format.

    So I want that each PCM1870A send me back 32bit data according to the clock it gets from the OMAPL138 in DSP format. The CPLD will pack all 8  streams of 32bit  to one TDM signal with 256bit to the OMAPL138.

    So, I asked again:

    Can I provide to BCK pin clock with 12.288MHz frequency in Audio TDM format (When the ADC config to be in Slave mode)?

    See bellow PCM1870A datasheet link:

    http://www.ti.com/product/pcm1870a

    I'd appreciate a quick answer.

    Thanks in advance,

    Itamar


     

  • Hi Itamar,

    Just to understand this correctly, you have all of your ADC lines going into the CPLD to create a TDM channel?

    I'm slightly confused by your wording because DSP mode and TDM are not the same. TDM is a way of doing I2S mode, left/right justified mode, and DSP mode for more than 2 channels. In order to do this, the device needs to be able to support an offset (and supporting registers) to correctly insert it's channels into the data stream. 

    Here is the view of a TDM channel in DSP mode (from the TLV320AIC3106 d/s page 28):

    As mentioned, the key to this is the offset. TDM in DSP mode will have the L and R channels of the first device, followed by the L and R channels of the second device (and so on and so forth) in that same word clock. Without TDM, DSP mode will only be able to have 2 channels, and it will have the L and R channels followed by 0s until the next WCLK pulse.

    Now, if I'm understanding this correctly, and you are using the CPLD to create the offset and put the data into a TDM channel, this will work - but you might want to look at an TLV320AIC3106 or similar family device that may be able to remove you from having to use a CPLD in your system.

    Please let me know if anything is unclear.

    Regards,

    ~John

     

     

  • Hey John,
    You are right!
    The shifts I'm going to do with the CPLD.
    The reason I chose this device and not the TLV320AIC3106 device, is I also need the internal amplifiers features to remove the need to add them externaly with there peripherals on my PCB.

    The inputs amplitude can be vary. Using the internal PCM1870A amps, I can set a fixed amplitude for PCM1870A sampling.

    So I'll ask my question again after we understood each other,

    The DSP format signals should be with the following configuration (I provide this signals from the OMAPL138):

    -The SCKI (F2 pin) pin should be at 12.288Mz.

    -The LRCK (E1 pin) pin should be at 48KHz (FS).

    -The BCK (F1 pin)  pin should be at 12.288Mz.

    Can I provide to BCK pin clock with 12.288MHz frequency in Audio TDM format (When the ADC config to be in Slave mode)?

    I'd appreciate a quick answer.

    Thanks in advance,

    Itamar


  • Hi Itamar,

    Glad we are on the same page!

    The PCM1870A supports a DSP mode (in slave mode) with an SCKI of 12.288 MHz, sampling frequency of 48KHz and a BCK of 256(Fs), which for 48KHz is 12.288 MHz. This can be verified by looking at the recommend operating conditions on page 2 of the d/s and the bottom of page 16 (Figure 14) on the d/s.

    I hope this answers your question. For your overall system, whether it will work correctly and TDM the outputs depends on the CPLD.

    Regards,

    ~John

  • Thank you very much John for your detail answer!

    Now I received my prototype card that contains the 8 PCM1870A (for support 16 channels of Microphones).

    I used SPI protocol to management the PCM1870A.

    I see that some of the PCM1870A don't respond to commands sent to.

    So I have some questions about:
    1) Is it possible to read PCM1870A registers in SPI protocol (I saw no reference to this issue in the datasheet)?

    2) Is there a certain process to be followed in order to initialize the PCM1870A will properly?

    3) Does the PCM1870A have internal PLL? if there is , it is the SCKI clock that operate this PLL?

    4) In Layout I routing in non-optimal way the SCKI clock. The clock arrived the PCM1870A SCKI pin with a little overshooting, is it can effect on the way of the PCM1870A respond to SPI commands?

    I'd appreciate to get an quick answer so that I could finish the R&D testing.

    Thanks in advance,
    Itamar

  • Hi Itamar,

    I appologize for the delay.

    Clocking is very important for the SPI to work properly. Have you probed the SPI lines to make sure that the signals are meeting the clocking requirements on page 20 of the datasheet?

    Is there any command/layout differences between the devices that are working as expected and the devices that are not working?

    There is no specific order of setting the registers to initialize the device. The PCM1780A has a clock manager that is operated off of the SCKI clock. I don't believe there is a way to read the registers in SPI, but I will get back to you on that early this week.

    Regards,

    ~John

     

     

     

  • Hi Itamar,

    Just wanted to update you that SPI is write only in this device.

    Regards,

    ~John

  • Hi,

    Thank you for your answer.

    in page 30 on datasheet there is register 85 (0x55).

    in this register there is SRST bit (System reset) ,which when is force to '1' system reset is enabled.

    On this page is written the following sentence:

    SRST: System Reset
    Default value: 0


    This bit is used to enable system reset. All circuits are reset by setting SRST = 1. After completing the reset
    sequence, SRST resets to 0 automatically.

    SRST = 0 Reset disabled (default)
    SRST = 1 Reset enabled

    How long does the process of system reset? That is, how long it takes SRST bit return to zero after it was forced to be one?

    Thanks in advance,

    Itamar

  • Hi Itamar,

    Unfortunately, we don't have that information. Without a current EVM, I also don't have a way to test this.

    Please let me know if you have any additional questions.

    Regards,

    ~John

  • Hello John,

    Further to our previous correspondence, I have another question:
    I configure the PCM1870A to work in Slave mode in DSP Audio format.
    The DSP format signals should be with the following configuration (I provide this signals from the OMAPL138):

    -The SCKI (F2 pin) pin should be at 12.288Mz.
    -The LRCK (E1 pin) pin should be at 48KHz (FS).
    -The BCK (F1 pin)  pin should be at 12.288Mz.

    **The ratio between SCKI to BCK was: 1

    Unfortunately it doesn't work! Although I did everything right by PCM1870A datasheet and you confirm that in your answer on my previews question.

    After a month of research on this issue, I was able to run the PCM1870A in the following configurations:

    Configuration number 1:

    - Master Mode
    -The SCKI (F2 pin) pin should be at 12.288Mz.
    -The LRCK (E1 pin) pin should be at 48KHz (FS).
    -The BCK (F1 pin) pin should be at 3.072Mz

    **The ratio between SCKI to BCK was: 4

    Configuration number 2:

    - Slave Mode
    -The SCKI (F2 pin) pin should be at 12.288Mz.
    -The LRCK (E1 pin) pin should be at 48KHz (FS).
    -The BCK (F1 pin) pin should be at 3.072Mz (64FS like Master mode).

    **The ratio between SCKI to BCK was: 4

    Configuration number 3:

    -Slave Mode
    -The SCKI (F2 pin) pin should be at 24Mz.
    -The LRCK (E1 pin) pin should be at 48KHz (FS).
    -The BCK (F1 pin) pin should be at 6Mz

    **The ratio between SCKI to BCK was: 4

     

    In addition, I tried to work in the following mode:

    -Slave Mode
    -The SCKI (F2 pin) pin should be at 24Mz.
    -The LRCK (E1 pin) pin should be at 48KHz (FS).
    -The BCK (F1 pin)  pin should be at 12Mz

    **The ratio between SCKI to BCK was: 2

    In this configuration I received a constant noise (2s-complement) on the PCM1870 data-out pin.

     

    So my new question to you is:

    Can you check these scenarios on your EVM with this configuration to confirm my results? 
    Or ask other TI-Employees whether they encountered scenarios that I raise?

    I'd appreciate a quick answer.

    Thanks in advance,

    Itamar

  • Hi Itamar,

    As I mentioned previously, I unfortunately don't have an EVM to test this out with. What are your register settings for registers 84-86 in your original configuration?

    Regards,

    ~John

  • Hi,

    Thank you for your quick response!

    The following PCM1870A register configuration is my configuration:

    • REGISTER 0x51 (ADC High Pass-Filter- 4Hz-48Khz, Soft Mute- Disabled, Audio Interface- DSP) = 0x5183
    • REGISTER 0x46 (Audio Interface- DSP) = 0x4603
    • REGISTER 0x5A (PG1, PG2 Gain Control - 0dB) = 0x5A00
    • REGISTER 0x49 (Analog Bias-Power Up) = 0x4980
    • REGISTER 0x56 (BCK- Input, Slave mode, zero cross- Disabled) = 0x5600
    • REGISTER 0x4A (VCOM- Power Up) = 0x4A01
    • REGISTER 0x54 (Slave Configuration) = 0x5401
    • REGISTER 0x52 (ADC, MCB, PG1,2,5,6- Power Up, D2S-Power Down) = 0x5237
    • REGISTER 0x57 (Analog input select (MUX3,4- SE, MUX1- AIN2L, MUX2- AIN2R) = 0x5722
    • REGISTER 0x4F (Volume for ADC input (L-ch)- 0dB) = 0x4F0C
    • REGISTER 0x50 (Volume for ADC input (R-ch)- 0dB) = 0x500C
    • REGISTER 0x53                                                     = 0x5300
    • REGISTER 0x55 (System reset- Disabled) = 0x5500
    • REGISTER 0x5C (Bass boost gain level (200 Hz)) = 0x5C00
    • REGISTER 0x5D (Middle boost gain level (1 kHz)) = 0x5D00
    • REGISTER 0x5E (Treble boost gain level (5 kHz)) = 0x5E00
    • REGISTER 0x5F (Sound effect source select, 3D sound) = 0x5F00
    • REGISTER 0x60 (2-stage notch filter, digital monaural mixing) = 0x60F0
    • REGISTER 0x61 (1st-stage notch filter lower coefficient (a1)) = 0x61FE
    • REGISTER 0x62 (1st-stage notch filter upper coefficient (a1)) = 0x62FF
    • REGISTER 0x63 (1st-stage notch filter lower coefficient (a2)) = 0x6301
    • REGISTER 0x64 (1st-stage notch filter upper coefficient (a2)) = 0x6400
    • REGISTER 0x65 (2nd-stage notch filter lower coefficient (a1)) = 0x65FE
    • REGISTER 0x66 (2nd-stage notch filter upper coefficient (a1)) = 0x66FF
    • REGISTER 0x67 (2nd-stage notch filter lower coefficient (a2)) = 0x6701
    • REGISTER 0x68 (2nd-stage notch filter upper coefficient (a2)) = 0x6800
    • REGISTER 0x7C (Mic boost) = 0x7C00

    Do you see any problem with my register configurations?

    Itamar

  • Hi Itamar,

    I'm looking into these settings. I will get back to you with what I find.

    Regards,

    ~John

  • Hi Itamar,

    I don't see any problem with your register configurations. However, I'm concerned about the clock meeting the timing requirements in the d/s. You are running BCLK at the maximum the device will allow, so the timing must be met with precision. Can forward a scope capture of the clocks?

     

    Regards,

    ~John