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DIT4192 master clock

Ralf Koschnicke
Prodigy 90 points

Other Parts Discussed in Thread: DIT4192

Hello,

I would like to provide the master clock for the DIT4192 directly from a clock distribution chip. But then SCLK, LRCLK and data coming from the ADC chip will have a delay of about 3ns compared with the direct clock signal because of a bus transceiver on the audio serial lines. In datasheet I find no information about the timing requirements of the master clock related to the audio serial input. Has someone experiences whether these 3ns offset could cause problems?

By the way, does someone know what exact function the separate master clock input has? Mainly I wonder what clock determines the clock quality of the AES output signal, the master clock, SCLK or LRCLK?

It would be very nice if someone could give me some more information please.

Best wishes

Ralf

  • 0
    TI__Guru**** 189401 points

    Hi, Ralf,

    Interesting questions!

    Would it be possible for you to delay the data by 3 ns as well so everything is still time-aligned?

    -d2

  • 0 in reply to Don Dapkus
    Prodigy 90 points

    Hi Don,

    thank you for your reply! Yes, I could send the master clock to a buffer like the other serial audio lines, too. But actually it would make no sense, using a high precision clock distribution fanout followed by a buffer. It makes the signal not better in that case, but maybe worse. If I got you right, your answer means: it would be better to time-align it, but it is not necessarily a problem, isn´t it?

    Essentially we are back at the question about what clock does determine the clock quality of the AES output. Maybe I should not care about the master clock quality at the DIT, at least not about this one additional buffer.

    Best,

    Ralf