Clocksource for PCM1794

SCK is the master clock for the PCM1794(A), which is not part of the I2S interface (it must be a multiple of the sampling rate - see Table 1 in the d/s). If you change the sampling rate or oversampling rate, you must also change the system clock.

The I2S clocks (BCK and LRCK) are typically generated by a host and must meet the specifications from page 15-17.

A single clock source is not sufficient, you'll have to have a I2S master somewhere in the system. Is there a uC with I2S interface in your design?

Okay, so my attached circuit won't work since I have to add a clock to the SCK Pin? An 24.576Mhz Crystal will work? What about my I2s circuit in general, is it okay?

I just removed the DIR9001 and just called this signal "ext"

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*push*

A 24.576MHz clock source is compatible with 32kHz, 48kHz, 96kHz and 192kHz sampling rates. It is not compatible with 44.1kHz (if that's what you require).

You cannot use a crystal directly. It has to be a oscillator with compatible logic levels and low phase jitter and noise (e.g. PLL1700 family). Ideally, the clock source should be the same clock that is used for your I2S master (what is you I2S master? Who generates LRCK_MAIN, DOUT_MAIN, BCK_MAIN ?