What is the jitter specification for the PCM4204 device to be able to guarantee the THD? The product is currently in planning and the decision on the clocking devices/scheme depends on the allowed jitter. The input system clock will be 24.576MHz and will possibly be generated via a PPL clock signal from an FPGA. The FPGA does not specify baseband jitter but has a approx a peak to peak jitter of 255.970 ps for the output clock of 24.576MHz.
Any jitter information (baseband, wideband, peak to peak ect) for the system clock SCKI or other clocks, bit clock BCK and word clock LRCK, would be appreciated.
I could not find the information in the data sheet, the only information I found was the spec for the PCM4104 which was SCK jitter <= 100ps. My assumption is they are the same but further clarification on this as well as other clocking jitter information would be much appreciated.
Sorry if this information is readily available and appreciate any help,
Neil
