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TLV320AIC33 slave mode ( DAC only ).

Sergei Vereskov
Intellectual 510 points
Other Parts Discussed in Thread: TLV320AIC33

Hello!

Please advise how to correctly use TLV320AIC33 in slave mode because datasheet pays very little attention to it.

I need to use only the DAC part of TLV320AIC33 to convert I2S ( DIN, BCLK, WCLK ) into analog audio.

Do I understand it correctly, that in slave mode ( as compared to master mode ) I have to do the following?

1). Connect BCLK, WCLK and DIN to TLV320AIC33 pins 38, 39, 40 respectively.

2). Select BCLK as the source for PLLCLK_IN in Register 102 on Page 0

3). Select BCLK, WCLK as inputs in Register 8 on Page 0

4). Calculate J, R, P to fulfill Fsref ( 48 kHz ) = BCLK ( 3.072 MHz ) x K x R / ( 2048 * P ) and set them into the corresponding registers.

My question is:

is WCLK ( connected to pin 39 ) used in DAC work or is it formed from BCLK using PLL as desribed in the above ( 4 )?

  • 0
    TI__Guru 61536 points

    1: correct
    2: correct. Also set CODEC_CLKIN to PLLDIV_OUT
    3: correct
    4: Calculate K,R,P:

    For Fs = 48kHz: CODEC_CLK = 256 * 48kHz = 12.288MHz.
    PLL_OUT = PLLDIV_OUT * 8 = CODEC_CLK * 8 = 98.304MHz.
    PLL_IN = BCLK = PLL_OUT * (P/K*R) = 3.072MHz
    (P/K*R) = 3.072MHz / 98.304MHz = 0.03125
    KR = P / 0.03125 = P * 32

    Example: Set P = 1, R = 1, K = 32 

    Test: Fs = (PLL_CLKIN * K * R) / (2048 * P) = 3.072MHz * 32 * 1 / (2048 * 1) = 48kHz

    Check:
    D = 0000 -> 2MHz <= 3.072MHz / 1 <= 20MHz -> ok.

    >>is WCLK ( connected to pin 39 ) used in DAC work or is it formed from BCLK using PLL as desribed in the above ( 4 )?

    If you choose to configure WCLK as an input, you will have to provide the signal externally. If you set it as an output, it will be derived from BCLK according your clock configuration (e.g. with the PLL settings above, it'll be generated at 48kHz)

     

     

  • 0 in reply to Dominik Hartl11
    Intellectual 510 points

    Hello!

    Thank You for Your quick reply.
    As long as I2S consists of 3 signals ( DIN, BCLK, WCLK ), then I have to feed all 3 of them into TLV320AIC33 and therefore set both BCLK, WCLK as inputs in Register 8 on Page 0.
    But why then do I have to use PLL to create another Fsref ( 48 kHz ) via setting J, R, P when WCLK=48 kHz is already present and if fed into TLV320AIC33?
    I'm afraid this will cause conflict of having two signals ( WCLK and Fsref ) of the same frequency ( 48 kHz ) , but out of phase.

    In other words, what settings should be made for TLV320AIC33, so that it could work as a simple audio DAC, such as UDA1334 for example?

    P.S. I chose TLV320AIC33 instead of UDA1334 because it has capless differential outputs and less BOM.

  • 0 in reply to Sergei Vereskov
    TI__Mastermind 28585 points

    The sample rate internal to the AIC33 is set by MCLK and the register settings. WCLK is just used to clock words out of the output buffer. WCLK must match the sample rate set internal to the AIC33 (Fsref).

    There is an app note here:

    http://www.ti.com/lit/an/slaa469/slaa469.pdf