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PCM5141/5142 with 8kHz sample frequency

Niels Andersen
Prodigy 40 points
Other Parts Discussed in Thread: PCM5142

Hi,

I am trying to configure PCM5142 to a sample rate of 8kHz. My system supplies the PCM5142 with an 8MHz  clock at SCK input pin. The datasheet says: "SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in software mode by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for example, using 12MHz to generate 44.1kHz (LRCK) and 2.8224MHz (BCK) )" so every thing should be fine. But figure 26 shows that SCK can only be devided with 1,2,3,...127,128 to provide BCKO and LRCKO.

My setup:
SCK input = 8MHz
Samplerate = 8kHz
PCM5142 runs as I2S master
Frequency of LRCKO = 8kHz
Frequency of BCKO = 512kHz

Kind regards,
Niels Andersen
Elcanic A/S

  • 0
    TI__Mastermind 28585 points

    Hi Niels,

    This will only be a problem if you have to operate the PCM as the master. Can you run it as a slave?

    Best Regards,

    dave

  • 0 in reply to Converter Apps
    Prodigy 40 points

    Hi Dave,

    I will try to run it as slave. I suppose that I need to configure the PLL and divider registers in software mode. Which settings for R, P, and K (J.D) would you recommend for this particular case. I have tried to figure it out, but I am getting illegal numbers when I try:

    Sample frequency is 8kHz. This gives a PLLCK on 98.304MHz according to table 12.

    Assuming "N" is the same as "PLL fs" in table 12. This gives "N" is 12288.

    Assuming that we ends up with a decimal number for K. This gives R =  1.

    (R*K)/P = PLLCK/PLLCKIN = (1*K)/P = 98.304M / 8M = 12.288

    Setting P equal to 1 gives K = 12.288. This is illegal since J = 12 and D = 2880. J should be in the range 4 and 11 when D != 0000

    Kind regards,
    Niels Andersen
    Elcanic A/S