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SRC4190 Clock

Shareef
Expert 1985 points
Other Parts Discussed in Thread: SRC4190

Hi All,

We have used SRC4190 in our design with both input and output ports in slave mode and both are in I2S modes.

Reference clock is 24.576MHz continuous clock and output port's clock is present always. We have an I2S source connected to input port whose bit clock and word clocks are not continuous. In other words, the bit clock and 48kHz WCLK stops for a few clock cycles and starts after some.

We have observed that output samples data from SRC4190 device is always mute (reading 0s). Can you please clarify if there is a minimum WCLK cycles required for SRC4190 to start giving out valid data.

Also what is the delay between input data and ASRC output data?

Regards,

Shareef

  • 0
    TI__Mastermind 27900 points

    Hi Shareef,

    In order to get a better picture of the problem could you provide more information on your setup, specifically what you have the pins connected to? Are you also able to provide any more detail on the signal statuses leading up to the part being muted and after? Does the part produce correct audio data out to begin with, and then after an interruption of the clock signals, does the output stay muted (all 0s) until you reset the device?

    I will look into the signal delay and get back to you when I am able to find some information.

    Justin

  • 0 in reply to Justin Bohr
    Expert 1985 points

    Hi Justin,

    Apologize for the delay. Please find my response below for your queries:

    1. Regarding setup, an I2S source of video decoder chip is connected to SRC4190 IC. This I2S source has bit clocks, word clocks and data which are ON for 30ms and OFF for 30ms (roughly). With this, the output data is mute for SRC4190 while its output port clocks are always present. (We expected the same audio present at input during the clocks ON time of 30ms to be available at SRC output, but we get mute)

    2. To make the SRC part work, reset is not required. Instead, if the clocks are made continuously available from the I2S source, then the output audio data from SRC4190 is valid.

    The other settings of SRC4190 are

    MODE[2:0] = 000, IFMT[2:0] = 001, OFMT[1:0]= 01, OWL[1:0] = 00, BYPASS mode is disabled.

    Hope this gives you details on the setup.

    Now my query is,

    a. Is this behavior expected of SRC4190 when the input clocks are not continuous as mentioned above? (In other words, what is the min WCLK cycle time of the SRC chip to process the data and output valid audio)

    b. what is the delay between input data and ASRC output data?

    Kindly provide your response.

    Regards,

    Shareef

  • 0 in reply to Shareef
    Expert 1985 points

    Hi Justin,

    Awaiting your response.

    Regards,

    Shareef

  • 0 in reply to Shareef
    TI__Mastermind 27900 points

    Hi Shareef,

    I apologize for the delay, I was out of the office the past few business days.

    Questions I have:

    1/2: So providing a continuous clock longer than 30 ms will cause the part to unmute? Do you have the RDY pin routed to the MUTE pin?

    A. I am still looking into more detailed information about the rate estimator that will dictate the muting response. I will get back when I have a definitive answer.

    B. In our data sheet we have Group Delay characteristics. These are measured in terms of seconds and relies on Fs. We have a specification for the digital interpolation filter: 

    LGRP = 0      102.53125/Fsin

    LGRP = 1      70.53125/Fsin 

    And the Digital decimation filter:

    36.46875/Fsout

    Depending on your application and which settings will change the delay, but these numbers will give you a good estimate for the delay of the input to output.

    Justin

  • 0 in reply to Justin Bohr
    Expert 1985 points

    Hi Justin,

    Thanks for getting back. Below is my response:

    1/2: Yes, providing a continuous clock does allow the part to un-mute and give out audio data as expected. The MUTE pin is tied to Ready pin in the design.

    A: I will wait for your reply on this.

    B: LGRP = 1 in our case. And both Fin and Fout are 48kHz. Then delay from input to output = 1.47ms (70.53/48k)? Can you please confirm if this is correct?

    Regards,

    Shareef

  • 0 in reply to Shareef
    Expert 1985 points

    Hi Justin,

    Do you have an update to share?

    Regards,

    Shareef

  • 0 in reply to Shareef
    TI__Mastermind 27900 points

    Hi Shareef,

    I do not have an update yet, I will reply as soon as I get an update.

    Justin

  • 0 in reply to Justin Bohr
    TI__Mastermind 27900 points

    Hi Shareef,

    The rate estimator will allow a valid output to go out as soon as it has a reference clock, a bit clock and a word clock that are withing the acceptable tolerances in the data sheet. This will bring the RDY pin low and should un-mute the part.

    I still don't have a clear picture of when it mutes for you. Does it stay muted if the clocks stop for 30ms and then turn on for 30ms and then turn off, you're saying that in that 30ms when the clocks were on, the output of the part stayed at all 0s? And if you were to leave the clocks on longer than 30ms the output would become un-muted?

    Have you tested this out on our EVM?

    Yes your calculation looks correct and would be around 1.47 ms for the delay.

    Justin

  • 0 in reply to Justin Bohr
    Expert 1985 points

    Hi Justin,

    Yes, the output stays all 0s when clock is not continuous. That is, it remains 0s even if clock is present for 30ms or not. What is the lock in period for the rate estimator? Is it more than 30ms?

    The output un-mutes automatically if the clocks are continuous.

    No, we have not tested this on EVM.

    Regards,

    Shareef

  • 0 in reply to Shareef
    Expert 1985 points

    Hi Justin, 

    Can you please confirm on the behavior of SRC chip for the scenario specified.

    Regards,

    Shareef

  • 0 in reply to Shareef
    TI__Mastermind 27900 points

    Hi Shareef,

    How long does it take for the output to unmute? Also is the time the output is muted directly related to the RDY pin state(which is attached to the MUTE pin) or does the RDY pin go low before the output is unmuted?

    Justin

  • 0 in reply to Justin Bohr
    Expert 1985 points

    Hi Justin,

    Apologize for the delay. It takes roughly 170ms of duration for READY signal to go low and output to un-mute after the clocks are made continuous. Is this also the setup/lock time for the Rate estimator block? Please confirm.

    In our case, the READY pin is connected directly to MUTE pin. So, muting of output is directly related to RDY pin.

    Regards,

    Shareef

  • 0 in reply to Shareef
    TI__Mastermind 27900 points

    Hi Shareef,

    Could you capture all the clocks and the ready pin on a scope at the different points in operation (running correctly, starting after stopped, when the part starts working again)?

    Justin

  • 0 in reply to Justin Bohr
    Expert 1985 points

    Hi Justin,

    Yes, I have verified this delay of 170 ms after clocks are continuous/discontinuous along with Ready signal on the scope.

    Regards,

    Shareef

  • 0 in reply to Shareef
    TI__Mastermind 27900 points

    Hi Shareef, 

    Can you send me the scope shots of the points I mentioned?

    Justin