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TPA2001D1, Ci, DC offset, Gain Setting issues in Single ended configurations.

Aditya Pandey
Prodigy 95 points
Other Parts Discussed in Thread: TPA2001D1

1. For Single ended configuration, what is V peak to peak that could be fed to INP terminal with INN grounded with cap?

2.For single ended configuration what is INP DC offset of amplifier, Is it 0V or some other DC offset is there which requires the preamplifier (Audio Codec SGTL5000) line out level to be clamped at the same level of TPA2001D1 INP line.

3.Can I connect Line out of preamplifier directly with INP (Sinlge ended configuration with INN grounded) with 1 DC blocking Capacitor in series?

4.Also in datasheet at page 8, it is written that " In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation " . My question : the input cap will take care of at what dc level the input signal is to be clamped or we have to take the DC level (at which the input signal is to be clamped) into consideration & calculate the value of cap. If we have to take the calculation into consideration, then please give me the algorithm for it.

5.Calculation of input capacitance requires input impedance & gain to be known. In datasheet at page : 8 it is given that " At the higher gain settings, the input impedance could increase as high as 115 kΩ. " But the table given just below of the above mentioned  statement shows that with increasing of gain, the input impedance decreases, which contradicts the above highlighted statement. Please give me the correct criteria to follow for calculation of input capacitance.

6.In  typical application diagram at page : 10, both Ci & Cbypass are given to be 1uF, but it is recommended to use cbypass 10 times greater than ci for pop reduction. Imagine a case in which my gain settings are such that , that Ci comes out to be 1uF, then Cbypass should be 10uF, but the range of Ci given is 0.1uF to 1uF & range of Cbypass given is 0.47uf to 1uf. So what should I do in this situation. Or what should I do typically?

  • 0
    TI__Intellectual 2285 points
    1. Vpk-pk = 0 - VDD (rail to rail)

    2. The value of the INP line from an amplifier point of view will be Vdd/2 because of the DC blocking capacitor which shift the signal..

    3. Yes, the TPA should be connected to the line out of your preamplifier with 1 DC blocking cap.

    4. Ci = 1 / 2*piZi fc (check datasheet)

    5. You are right, there is a mistake..
    it should rather be "At the lower gain settings, the input impedance could increase as high as 72 kΩ" because G = Rf/ Rin.
    We will change it in the future, thanks.. So the right reference for you is the Table 1. Gain settings

    6. Basically, to avoid pop noise when the input it turns on, the bypass capacitor should be higher than the input Capacitor..
    In the situation you advertise, it depends..
    - If you want to have the best THD + N performance, then you should choose a value of capacitor in the 0.47-µF to 1-µF range, but the Cbypass should always be higher or equal to Ci.
    - To have minimal pop, Cbypass should be 10 times larger than Ci

    Regards,
    Mohamed Hellal