TAS5631B PBTL setting

Hello Shibatani-san,

We will take a look at these questions and give you answers ASAP.

Best regards,

Tuan

Hello Shibatani-san,

Sorry for the delay.  I really like how you ask questions.  They are very precise.  Please see the answers below.

Q1  

When does TAS5631B latch the Mode status (M3=M1=0, M2=1) ?

Is it  on the start up at GVDD(=12V) ?   or  start up at PVDD?

My customer set  PVDD first, then M3/M2/M1 set, then set GVDD.

We are concerned about  it may be cause any problem.

Please let me know the timing of M3/M2/M1 latching for mode selection.

 Answer 1:

-Mx pins are logic pins and are powered by an internal LDO via the VDD (12V).

-It is okay to set the PVDD first.  You must keep the reset pin low during power up until all power rails are good.  This keeps all the logic in check.

-Once the power is up, mode pins must be set before reset is de-asserted.

Q2

Data sheet Page 6 TYPICAL Block　Diagram　says  M3/M2/M1 should be set  by Hard wire mode control

That is to say, to control M3~M1, any I/O expander i.e.,TCA6408  's output  is not recommended for changing the mode from BTL/PBTL?

My client 's power up sequence is  I/O expander is setting  M3~M1 for 1/0/1 first  and then GVDD is set...

Answer 2:

This is fine as long as all of the following conditions are met:

-Mode pins set the power stage operation: SE, BTL, or PBTL.  None of these modes can be changed on the fly.  This is why it must be hard wired.  However, if you assert reset, then set the modes, then de-assert reset and keep reset de-asserted for the entire operation.

-Be sure that reset is pulled-down just in case there are power glitches.  When there is a power glitch, for sure the mode pin logic is unknown.  This is not good.

-Be sure reset is pulled-down before the PVDD and VDD power are applied.  The best way is having a 100kOhm to ground.  As you can see, this operation is delicate and we do not know how the customer configures logic.  It is best for these mode pins to be hard wired.

Q3

In case  PBTL,  we know we should set INPUT_C=VREG (Or GND), INPUT_D=GND. ( Data sheet page3 and page 17)

But my customer ties TAS5508 PWM1+ with INPUT_C and GND( thru switch)  together ( wired Oring).

Please see attached  jpg.  ( PWM1-and INPUT_D is same manner.)

Also,  TAS5508B PWM1+=PWM2+, PWM1-=PWM2-,

Is this not -recommended? 

Or , is it OK because TAS5631 neglects  INPUT_C & D if PBTL mode.

If it is not recommended, what kind of  the problem may occur?

Answer 3:

We have not tested the input pins through a switch.  There are many switch variations and parasitic effects.  Also, the input pins are for AC signals and should be AC ground (via a small cap 0.1uF).  My recommendation is:  assert reset, then ground the inputs via caps and switch, then de-assert reset for normal operation.  Again, this should not be done on the fly (during operation).  Pop noise or audio artifacts may occur if it is not handled correctly.

The recommendations on the above answers must be tested in the customer's system to be sure of its operations.

Best regards,

Tuan

Dear Tuan-san,Thank you for your answer, and I appreciate that.
In regard to Q1 and Q2, I understood your answer. Thank you very much.
In regard to Q3, please allow me to have question again.
I don't know about the meaning of AC ground.
In the TAS5631B data sheet sles263c.pdf page3, INPUT_C and INPUT_D= 0 for AD mode ( I think AC mode is typo of data sheet)
This is GND, not AC GND.If my understanding is wrong, please correct me.
Thank you and with my best regards

Hello Shibatani-san,

You are absolutely right.  These are PWM input pins and is grounded (0).  Sorry, my mistake ... I was revising TAS5630B data sheet, which has analog inputs and I made a mistake.  This is TAS5631B.

Thank you,

Tuan

Dear Tuan-san,

Thank you for your reply  and sorry my reply was in delay.

Best Regards