PCM3070, MCLK=6.1442MHz

Update: I was able to increase the MCLK to 24.5769. Now, I am able to use the PLL Calculator to generate the required values. However, it would still be nice to understand how the figures were derived.

Thanks.

Hi Phil,

So there are a couple things you need to do when trying to use the PLL manually.

-Configure the clock tree to use the PLL as a source for every clock, there might be some that default to SCK or some other source.
-All clocks are multiples of the sampling frequency
-DSP clock allows enough cycles per sample to accomplish program (1024FS means 1024 cycles for DSP code)
-ADC clock should be at least 64FS

With the above in mind, section 2.6 in the PCM3070 Reference Guide talks about the PLL and specifically 2.6.1 talks about the calculations. There are also tables of examples for certain sample frequencies and master clocks. When setting up a custom PLL seting, try matching the closest example in the table and then changing what is needed.

You said you tried the PLL calculator in the CS GUI, this should give you correct PLL settings for the desired sampling rate and input clock. Could you share the settings you tried?

Justin

// Known Information:
// MCLK = 24.5769 MHz
// BCLK = 3.0721 MHz
// WCLK = 48 KHz
// AVDD = 1.78 V
// DVDD = 1.78 V

// Assumptions:
// DOSR = 128
// AOSR = 128
// ADC_FS = 48 KHz

// Results from PLL Calculator
// R = 1
// P = 2
// J.D = 7.9997
// MDAC/MADC = 2
// NDAC/NADC = 8
// Actual FS = 47999.9577, % Error 0.00008803

Hi Phil,

What performance are you getting THD wise?

Justin